Datasheet Texas Instruments SN74LVT18512 — Ficha de datos

FabricanteTexas Instruments
SerieSN74LVT18512
Datasheet Texas Instruments SN74LVT18512

Dispositivos de prueba de escaneo ABT de 3.3 V con transceptores de bus universal de 18 bits

Hojas de datos

3.3-V ABT Scan Test Devices With 18-Bit Universal Bus Transceivers datasheet
PDF, 762 Kb, Archivo publicado: oct 1, 1997
Extracto del documento

Precios

Estado

SN74LVT18512DGGR
Estado del ciclo de vidaActivo (Recomendado para nuevos diseños)
Disponibilidad de muestra del fabricanteNo

Embalaje

SN74LVT18512DGGR
N1
Pin64
Package TypeDGG
Industry STD TermTSSOP
JEDEC CodeR-PDSO-G
Package QTY2000
CarrierLARGE T&R
Device MarkingLVT18512
Width (mm)6.1
Length (mm)17
Thickness (mm)1.15
Pitch (mm).5
Max Height (mm)1.2
Mechanical DataDescargar

Paramétricos

Parameters / ModelsSN74LVT18512DGGR
SN74LVT18512DGGR
Bits18
F @ Nom Voltage(Max), Mhz160
ICC @ Nom Voltage(Max), mA24
Operating Temperature Range, C-40 to 85
Output Drive (IOL/IOH)(Max), mA64/-32
Package GroupTSSOP
Package Size: mm2:W x L, PKG64TSSOP: 138 mm2: 8.1 x 17(TSSOP)
RatingCatalog
Technology FamilyLVT
VCC(Max), V3.6
VCC(Min), V2.7
Voltage(Nom), V3.3
tpd @ Nom Voltage(Max), ns4.9

Plan ecológico

SN74LVT18512DGGR
RoHSObediente

Notas de aplicación

  • Programming CPLDs Via the 'LVT8986 LASP
    PDF, 819 Kb, Archivo publicado: nov 1, 2005
    This application report summarizes key information required for understanding the 'LVT8986 linking addressable scan ports (LASPs) multidrop addressable IEEE Std 1149.1 (JTAG) test access port (TAP) transceiver. This report includes information about the 'LVT8986 secondary TAPs, bypass and linking shadow protocol, scan-path description languages, serial vector format files, and an example of how to
  • LVT Family Characteristics (Rev. A)
    PDF, 98 Kb, Revisión: A, Archivo publicado: marzo 1, 1998
    To address the need for a complete low-voltage interface solution, Texas Instruments has developed a new generation of logic devices capable of mixed-mode operation. The LVT series relies on a state-of-the-art submicron BiCMOS process to provide up to a 90% reduction in static power dissipation over ABT. LVT devices solve the system need for a transparent seam between the low-voltage and 5-V secti
  • LVT-to-LVTH Conversion
    PDF, 84 Kb, Archivo publicado: dic 8, 1998
    Original LVT devices that have bus hold have been redesigned to add the High-Impedance State During Power Up and Power Down feature. Additional devices with and without bus hold have been added to the LVT product line. Design guidelines and issues related to the bus-hold features, switching characteristics, and timing requirements are discussed.

Linea modelo

Serie: SN74LVT18512 (1)

Clasificación del fabricante

  • Semiconductors> Logic> Specialty Logic> Boundary Scan (JTAG) Logic