Datasheet Texas Instruments SN74LVTH162374 — Ficha de datos

FabricanteTexas Instruments
SerieSN74LVTH162374
Datasheet Texas Instruments SN74LVTH162374

Flip-Flops tipo D de 3.3 bits y 16 bits ABT activados por borde con salidas de 3 estados

Hojas de datos

SN54LVTH162374, SN74LVTH162374 datasheet
PDF, 942 Kb, Revisión: M, Archivo publicado: nov 18, 2006
Extracto del documento

Precios

Estado

74LVTH162374DGGRG474LVTH162374ZQLR74LVTH162374ZRDRSN74LVTH162374DGGRSN74LVTH162374DLSN74LVTH162374DLRSN74LVTH162374KR
Estado del ciclo de vidaActivo (Recomendado para nuevos diseños)Activo (Recomendado para nuevos diseños)Activo (Recomendado para nuevos diseños)Activo (Recomendado para nuevos diseños)Activo (Recomendado para nuevos diseños)Activo (Recomendado para nuevos diseños)Obsoleto (El fabricante ha interrumpido la producción del dispositivo)
Disponibilidad de muestra del fabricanteNoNoNoNoNoNoNo

Embalaje

74LVTH162374DGGRG474LVTH162374ZQLR74LVTH162374ZRDRSN74LVTH162374DGGRSN74LVTH162374DLSN74LVTH162374DLRSN74LVTH162374KR
N1234567
Pin48565448484856
Package TypeDGGZQLZRDDGGDLDLGQL
Industry STD TermTSSOPBGA MICROSTAR JUNIORBGA MICROSTAR JUNIORTSSOPSSOPSSOPBGA MICROSTAR JUNIOR
JEDEC CodeR-PDSO-GR-PBGA-NR-PBGA-NR-PDSO-GR-PDSO-GR-PDSO-GR-PBGA-N
Package QTY2000100010002000251000
CarrierLARGE T&RLARGE T&RLARGE T&RLARGE T&RTUBELARGE T&R
Device MarkingLVTH162374LL2374LL2374LVTH162374LVTH162374LVTH162374
Width (mm)6.14.55.56.17.497.494.5
Length (mm)12.57812.515.8815.887
Thickness (mm)1.15.75.81.152.592.59.75
Pitch (mm).5.65.8.5.635.635.65
Max Height (mm)1.211.21.22.792.791
Mechanical DataDescargarDescargarDescargarDescargarDescargarDescargarDescargar

Paramétricos

Parameters / Models74LVTH162374DGGRG4
74LVTH162374DGGRG4
74LVTH162374ZQLR
74LVTH162374ZQLR
74LVTH162374ZRDR
74LVTH162374ZRDR
SN74LVTH162374DGGR
SN74LVTH162374DGGR
SN74LVTH162374DL
SN74LVTH162374DL
SN74LVTH162374DLR
SN74LVTH162374DLR
SN74LVTH162374KR
SN74LVTH162374KR
3-State OutputYesYesYesYesYesYesYes
Approx. Price (US$)0.52 | 1ku
Bits161616161616
Bits(#)16
F @ Nom Voltage(Max), Mhz160160160160160160
F @ Nom Voltage(Max)(Mhz)160
ICC @ Nom Voltage(Max), mA555555
ICC @ Nom Voltage(Max)(mA)5
Input TypeTTL
Operating Temperature Range, C-40 to 85-40 to 85-40 to 85-40 to 85-40 to 85-40 to 85
Operating Temperature Range(C)-40 to 85
Output Drive (IOL/IOH)(Max), mA12/-1212/-1212/-1212/-1212/-1212/-12
Output Drive (IOL/IOH)(Max)(mA)12/-12
Output TypeTTL
Package GroupTSSOPBGA MICROSTAR JUNIORBGA MICROSTAR JUNIORTSSOPSSOPSSOPBGA MICROSTAR JUNIOR
Package Size: mm2:W x L, PKG48TSSOP: 101 mm2: 8.1 x 12.5(TSSOP)56BGA MICROSTAR JUNIOR: 32 mm2: 4.5 x 7(BGA MICROSTAR JUNIOR)56BGA MICROSTAR JUNIOR: 32 mm2: 4.5 x 7(BGA MICROSTAR JUNIOR)48TSSOP: 101 mm2: 8.1 x 12.5(TSSOP)48SSOP: 164 mm2: 10.35 x 15.88(SSOP)48SSOP: 164 mm2: 10.35 x 15.88(SSOP)
Package Size: mm2:W x L (PKG)56BGA MICROSTAR JUNIOR: 32 mm2: 4.5 x 7(BGA MICROSTAR JUNIOR)
RatingCatalogCatalogCatalogCatalogCatalogCatalogCatalog
Schmitt TriggerNoNoNoNoNoNoNo
Technology FamilyLVTLVTLVTLVTLVTLVTLVT
VCC(Max), V3.63.63.63.63.63.6
VCC(Max)(V)3.6
VCC(Min), V2.72.72.72.72.72.7
VCC(Min)(V)2.7
Voltage(Nom), V3.33.33.33.33.33.3
Voltage(Nom)(V)3.3
tpd @ Nom Voltage(Max), ns5.35.35.35.35.35.3
tpd @ Nom Voltage(Max)(ns)5.3

Plan ecológico

74LVTH162374DGGRG474LVTH162374ZQLR74LVTH162374ZRDRSN74LVTH162374DGGRSN74LVTH162374DLSN74LVTH162374DLRSN74LVTH162374KR
RoHSObedienteObedienteObedienteObedienteObedienteObedienteDesobediente
Pb gratisNo

Notas de aplicación

  • LVT Family Characteristics (Rev. A)
    PDF, 98 Kb, Revisión: A, Archivo publicado: marzo 1, 1998
    To address the need for a complete low-voltage interface solution, Texas Instruments has developed a new generation of logic devices capable of mixed-mode operation. The LVT series relies on a state-of-the-art submicron BiCMOS process to provide up to a 90% reduction in static power dissipation over ABT. LVT devices solve the system need for a transparent seam between the low-voltage and 5-V secti
  • LVT-to-LVTH Conversion
    PDF, 84 Kb, Archivo publicado: dic 8, 1998
    Original LVT devices that have bus hold have been redesigned to add the High-Impedance State During Power Up and Power Down feature. Additional devices with and without bus hold have been added to the LVT product line. Design guidelines and issues related to the bus-hold features, switching characteristics, and timing requirements are discussed.
  • Bus-Hold Circuit
    PDF, 418 Kb, Archivo publicado: feb 5, 2001
    When designing systems that include CMOS devices, designers must pay special attention to the operating condition in which all of the bus drivers are in an inactive, high-impedance condition (3-state). Unless special measures are taken, this condition can lead to undefined levels and, thus, to a significant increase in the device?s power dissipation. In extreme cases, this leads to oscillation of
  • 16-Bit Widebus Logic Families in 56-Ball 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B)
    PDF, 895 Kb, Revisión: B, Archivo publicado: mayo 22, 2002
    TI?s 56-ball MicroStar Jr.E package registered under JEDEC MO-225 has demonstrated through modeling and experimentation that it is an optimal solution for reducing inductance and capacitance improving thermal performance and minimizing board area usage in integrated bus functions. Multiple functions released in the 56-ball MicroStar Jr.E package have superior performance characteristics compa
  • Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A)
    PDF, 105 Kb, Revisión: A, Archivo publicado: agosto 1, 1997
    The spectrum of bus-interface devices with damping resistors or balanced/light output drive currently offered by various logic vendors is confusing at best. Inconsistencies in naming conventions and methods used for implementation make it difficult to identify the best solution for a given application. This report attempts to clarify the issue by looking at several vendors? approaches and discussi
  • Understanding Advanced Bus-Interface Products Design Guide
    PDF, 253 Kb, Archivo publicado: mayo 1, 1996
  • Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices
    PDF, 209 Kb, Archivo publicado: mayo 10, 2002
    Many telecom and networking applications require that cards be inserted and extracted from a live backplane without interrupting data or damaging components. To achieve this interface terminals of the card must be electrically isolated from the bus system during insertion or extraction from the backplane. To facilitate this Texas Instruments provides bus-interface and logic devices with features
  • Live Insertion
    PDF, 150 Kb, Archivo publicado: oct 1, 1996
    Many applications require the ability to exchange modules in electronic systems without removing the supply voltage from the module (live insertion). For example an electronic telephone exchange must always remain operational even during module maintenance and repair. To avoid damaging components additional circuitry modifications are necessary. This document describes in detail the phenomena tha
  • Input and Output Characteristics of Digital Integrated Circuits
    PDF, 1.7 Mb, Archivo publicado: oct 1, 1996
    This report contains a comprehensive collection of the input and output characteristic curves of typical integrated circuits from various logic families. These curves go beyond the information given in data sheets by providing additional details regarding the characteristics of the components. This knowledge is particularly useful when for example a decision must be made as to which circuit shou
  • Power-Up Behavior of Clocked Devices (Rev. A)
    PDF, 34 Kb, Revisión: A, Archivo publicado: feb 6, 2015

Linea modelo

Clasificación del fabricante

  • Semiconductors> Logic> Flip-Flop/Latch/Register> D-Type Flip-Flop