Datasheet Texas Instruments SN74LVTH32374 — Ficha de datos

Fabricante	Texas Instruments
Serie	SN74LVTH32374

Flip-Flop tipo D de 32 bits ABT de 32 bits activado por borde con salidas de 3 estados

Hojas de datos

Descargar

PDF, 728 Kb, Revisión: D, Archivo publicado: agosto 10, 2007

Extracto del documento

SN74LVTH32374
3.3-V ABT 32-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH 3-STATE OUTPUTS www.ti.com SCBS752D вЂ“ SEPTEMBER 2000 вЂ“ REVISED AUGUST 2007 FEATURES 1 Member of the Texas Instruments
Widebus+в„ў Family State-of-the-Art Advanced BiCMOS
Technology (ABT) Design for 3.3-V Operation
and Low Static-Power Dissipation Typical VOLP (Output Ground Bounce) VCC.
The package thermal impedance is calculated in accordance with JESD 51-7. Submit Documentation Feedback Copyright В© 2000вЂ“2007, Texas Instruments Incorporated Product Folder Link(s): SN74LVTH32374 3 SN74LVTH32374
3.3-V ABT 32-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH 3-STATE OUTPUTS www.ti.com SCBS752D вЂ“ SEPTEMBER 2000 вЂ“ REVISED AUGUST 2007 Recommended Operating Conditions (1)
MIN MAX 2.7 3.6 UNIT VCC Supply voltage VIH High-level input voltage VIL Low-level input voltage VI Input voltage 5.5 V IOH High-level output current вЂ“32 mA IOL Low-level output current 64 mA О”t/О”v Input transition rise or fall rate О”t/О”VCC Power-up ramp rate 200 TA Operating free-air temperature вЂ“40 (1) 4 2 V
0.8 Outputs enabled V 10 V ns/V
Ојs/V 85 В°C All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004. Submit Documentation Feedback Copyright В© 2000вЂ“2007, Texas Instruments Incorporated Product Folder Link(s): SN74LVTH32374 SN74LVTH32374
3.3-V ABT 32-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH 3-STATE OUTPUTS www.ti.com SCBS752D вЂ“ SEPTEMBER 2000 вЂ“ REVISED AUGUST 2007 Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
VIK
VOH TEST CONDITIONS
VCC = 2.7 V, II = вЂ“18 mA VCC = 2.7 V to 3.6 V, IOH = вЂ“100 ОјA VCC = 2.7 V, IOH = вЂ“8 mA VCC = 3 V, IOH = вЂ“32 mA VCC = 2.7 V
VOL
VCC = 3 V Control inputs II Data inputs
Ioff TYP (1) MAX UNIT вЂ“1.2 V VCC вЂ“ 0.2 …

Precios

Estado

	SN74LVTH32374ZKER
Estado del ciclo de vida	Activo (Recomendado para nuevos diseños)
Disponibilidad de muestra del fabricante	Sí

Embalaje

	SN74LVTH32374ZKER
N	1
Pin	96
Package Type	ZKE
Industry STD Term	BGA MICROSTAR
JEDEC Code	R-PBGA-N
Package QTY	1000
Carrier	LARGE T&R
Device Marking	HV374
Width (mm)	5.5
Length (mm)	13.5
Thickness (mm)	.85
Pitch (mm)	.8
Max Height (mm)	1.4
Mechanical Data	Descargar

Paramétricos

Parameters / Models	SN74LVTH32374ZKER
3-State Output	Yes
Bits	32
F @ Nom Voltage(Max), Mhz	160
ICC @ Nom Voltage(Max), mA	10
Operating Temperature Range, C	-40 to 85
Output Drive (IOL/IOH)(Max), mA	64/-32
Package Group	LFBGA
Package Size: mm2:W x L, PKG	96LFBGA: 74 mm2: 5.5 x 13.5(LFBGA)
Rating	Catalog
Schmitt Trigger	No
Technology Family	LVT
VCC(Max), V	3.6
VCC(Min), V	2.7
Voltage(Nom), V	3.3
tpd @ Nom Voltage(Max), ns	4.5

Plan ecológico

	SN74LVTH32374ZKER
RoHS	Obediente

Notas de aplicación

Descargar
LVT Family Characteristics (Rev. A)
PDF, 98 Kb, Revisión: A, Archivo publicado: marzo 1, 1998
To address the need for a complete low-voltage interface solution, Texas Instruments has developed a new generation of logic devices capable of mixed-mode operation. The LVT series relies on a state-of-the-art submicron BiCMOS process to provide up to a 90% reduction in static power dissipation over ABT. LVT devices solve the system need for a transparent seam between the low-voltage and 5-V secti
Descargar
LVT-to-LVTH Conversion
PDF, 84 Kb, Archivo publicado: dic 8, 1998
Original LVT devices that have bus hold have been redesigned to add the High-Impedance State During Power Up and Power Down feature. Additional devices with and without bus hold have been added to the LVT product line. Design guidelines and issues related to the bus-hold features, switching characteristics, and timing requirements are discussed.
Descargar
Bus-Hold Circuit
PDF, 418 Kb, Archivo publicado: feb 5, 2001
When designing systems that include CMOS devices, designers must pay special attention to the operating condition in which all of the bus drivers are in an inactive, high-impedance condition (3-state). Unless special measures are taken, this condition can lead to undefined levels and, thus, to a significant increase in the device?s power dissipation. In extreme cases, this leads to oscillation of

Linea modelo

Serie: SN74LVTH32374 (1)

SN74LVTH32374ZKER

Clasificación del fabricante

Semiconductors> Logic> Flip-Flop/Latch/Register> D-Type Flip-Flop