Datasheet Texas Instruments THS5661A — Ficha de datos

FabricanteTexas Instruments
SerieTHS5661A
Datasheet Texas Instruments THS5661A

Convertidor digital a analógico (DAC) de 12 bits y 125 MSPS

Hojas de datos

12-Bit, 125 MSPS, CommsDAC Digital-to-Analog Converter datasheet
PDF, 960 Kb, Revisión: B, Archivo publicado: sept 25, 2002
Extracto del documento

Precios

Estado

THS5661AIDWTHS5661AIPWTHS5661AIPWR
Estado del ciclo de vidaActivo (Recomendado para nuevos diseños)Activo (Recomendado para nuevos diseños)Activo (Recomendado para nuevos diseños)
Disponibilidad de muestra del fabricanteNoNo

Embalaje

THS5661AIDWTHS5661AIPWTHS5661AIPWR
N123
Pin282828
Package TypeDWPWPW
Industry STD TermSOICTSSOPTSSOP
JEDEC CodeR-PDSO-GR-PDSO-GR-PDSO-G
Package QTY20502000
CarrierTUBETUBELARGE T&R
Device MarkingTHS5661AITJ5661AITJ5661AI
Width (mm)7.54.44.4
Length (mm)17.99.79.7
Thickness (mm)2.3511
Pitch (mm)1.27.65.65
Max Height (mm)2.651.21.2
Mechanical DataDescargarDescargarDescargar

Paramétricos

Parameters / ModelsTHS5661AIDW
THS5661AIDW
THS5661AIPW
THS5661AIPW
THS5661AIPWR
THS5661AIPWR
ArchitectureCurrent SourceCurrent SourceCurrent Source
DAC Channels111
InterfaceParallel CMOSParallel CMOSParallel CMOS
Interpolation1x1x1x
Operating Temperature Range, C-40 to 85-40 to 85-40 to 85
Package GroupSOICTSSOPTSSOP
Package Size: mm2:W x L, PKG28SOIC: 184 mm2: 10.3 x 17.9(SOIC)28TSSOP: 62 mm2: 6.4 x 9.7(TSSOP)28TSSOP: 62 mm2: 6.4 x 9.7(TSSOP)
Power Consumption(Typ), mW175175175
RatingCatalogCatalogCatalog
Resolution, Bits121212
SFDR, dB595959
Sample / Update Rate, MSPS125125125

Plan ecológico

THS5661AIDWTHS5661AIPWTHS5661AIPWR
RoHSObedienteObedienteObediente

Notas de aplicación

  • Using TI FIFOs to Interface High-Speed Data Converters With TI TMS320 DSPs
    PDF, 249 Kb, Archivo publicado: jun 8, 2001
    Most high-speed data converters cannot be connected directly to a digital signal processor (DSP). The required transfer rates would tie up most of the DSP's I/O bandwidth. A FIFO is an appropriate solution for this problem because it can buffer a large block of data, and the DSP can read data from the FIFO in a burst mode. This is much more efficient compared to single reads for every sampled valu
  • Wideband Complementary Current Output DAC Single-Ended Interface
    PDF, 597 Kb, Archivo publicado: jun 21, 2005
    High-speed digital-to-analog converters (DACs) most often use a transformer-coupled output stage. In applications where this configuration is not practical, a single op ampdifferential to single-ended stage has often been used. This application note steps through the exact design equations required to achieve gain matching from each output as well as a matched input impedance to each of the DA
  • Noise Analysis for High Speed Op Amps (Rev. A)
    PDF, 256 Kb, Revisión: A, Archivo publicado: enero 17, 2005
    As system bandwidths have increased an accurate estimate of the noise contribution for each element in the signal channel has become increasingly important. Many designers are not however particularly comfortable with the calculations required to predict the total noise for an op amp or in the conversions between the different descriptions of noise. Considerable inconsistency between manufactu

Linea modelo

Clasificación del fabricante

  • Semiconductors> Data Converters> Digital-to-Analog Converters (DACs)> High Speed DACs (>10MSPS)