Datasheet Texas Instruments TLV571 — Ficha de datos

FabricanteTexas Instruments
SerieTLV571
Datasheet Texas Instruments TLV571

8 bits, 1.25 MSPS Single Ch., Configuración de hardware, baja potencia con Auto o S / W PowerDown

Hojas de datos

2.7 V To 5.5 V, 1-Channel, 8-Bit Parallel ADC datasheet
PDF, 515 Kb, Revisión: A, Archivo publicado: feb 9, 2000
Extracto del documento

Precios

Estado

TLV571IDWTLV571IDWG4TLV571IPW
Estado del ciclo de vidaActivo (Recomendado para nuevos diseños)Activo (Recomendado para nuevos diseños)Activo (Recomendado para nuevos diseños)
Disponibilidad de muestra del fabricanteNoNoNo

Embalaje

TLV571IDWTLV571IDWG4TLV571IPW
N123
Pin242424
Package TypeDWDWPW
Industry STD TermSOICSOICTSSOP
JEDEC CodeR-PDSO-GR-PDSO-GR-PDSO-G
Package QTY252560
CarrierTUBETUBETUBE
Device MarkingTLV571ITLV571ITY571
Width (mm)7.57.54.4
Length (mm)15.415.47.8
Thickness (mm)2.352.351
Pitch (mm)1.271.27.65
Max Height (mm)2.652.651.2
Mechanical DataDescargarDescargarDescargar

Paramétricos

Parameters / ModelsTLV571IDW
TLV571IDW
TLV571IDWG4
TLV571IDWG4
TLV571IPW
TLV571IPW
# Input Channels111
Analog Voltage AVDD(Max), V5.55.55.5
Analog Voltage AVDD(Min), V2.72.72.7
ArchitectureSARSARSAR
Digital Supply(Max), V5.55.55.5
Digital Supply(Min), V2.72.72.7
INL(Max), +/-LSB0.50.50.5
Input Range(Max), V5.55.55.5
Input TypeSingle-EndedSingle-EndedSingle-Ended
Integrated FeaturesOscillatorOscillatorOscillator
InterfaceParallelParallelParallel
Multi-Channel ConfigurationN/AN/AN/A
Operating Temperature Range, C-40 to 85-40 to 85-40 to 85
Package GroupSOICSOICTSSOP
Package Size: mm2:W x L, PKG24SOIC: 160 mm2: 10.3 x 15.5(SOIC)24SOIC: 160 mm2: 10.3 x 15.5(SOIC)24TSSOP: 50 mm2: 6.4 x 7.8(TSSOP)
Power Consumption(Typ), mW121212
RatingCatalogCatalogCatalog
Reference ModeExtExtExt
Resolution, Bits888
SINAD, dB494949
SNR, dB494949
Sample Rate (max), SPS1.25MSPS1.25MSPS1.25MSPS
Sample Rate(Max), MSPS1.251.251.25
THD(Typ), dB-64-64-64

Plan ecológico

TLV571IDWTLV571IDWG4TLV571IPW
RoHSObedienteObedienteObediente

Notas de aplicación

  • Determining Minimum Acquisition Times for SAR ADCs, part 2
    PDF, 215 Kb, Archivo publicado: marzo 17, 2011
    The input structure circuit of a successive-approximation register analog-to-digital converter (SAR ADC) incombination with the driving circuit forms a transfer function that can be used to determine minimum acquisition times for different types of applied input signals. This application report, which builds on Determining Minimum Acquisition Times for SAR ADCs When a Step Function is Applied to

Linea modelo

Clasificación del fabricante

  • Semiconductors> Data Converters> Analog-to-Digital Converters (ADCs)> Precision ADCs (<=10MSPS)