Datasheet Texas Instruments TMS320C6670 — Ficha de datos

FabricanteTexas Instruments
SerieTMS320C6670
Datasheet Texas Instruments TMS320C6670

Sistema en chip multinúcleo fijo y de punto flotante

Hojas de datos

TMS320C6670 Multicore Fixed and Floating-Point System-on-Chip datasheet
PDF, 2.4 Mb, Revisión: D, Archivo publicado: marzo 7, 2012
Extracto del documento

Precios

Estado

TMS320C6670ACYP2TMS320C6670ACYPATMS320C6670ACYPA2TMS320C6670AXCYPTMS320C6670AXCYP2TMS320C6670AXCYPATMS320C6670AXCYPA2TMS320C6670CYPTMS320C6670CYP2TMS320C6670CYPATMS320C6670CYPA2TMS320C6670XCPY2TMS320C6670XCYPTMS320C6670XCYPATMS320C6670XCYPA2TMX320C6670AXCYPTMX320C6670CYP
Estado del ciclo de vidaActivo (Recomendado para nuevos diseños)Activo (Recomendado para nuevos diseños)Activo (Recomendado para nuevos diseños)Activo (Recomendado para nuevos diseños)Activo (Recomendado para nuevos diseños)Activo (Recomendado para nuevos diseños)Activo (Recomendado para nuevos diseños)Obsoleto (El fabricante ha interrumpido la producción del dispositivo)Obsoleto (El fabricante ha interrumpido la producción del dispositivo)Obsoleto (El fabricante ha interrumpido la producción del dispositivo)Activo (Recomendado para nuevos diseños)Activo (Recomendado para nuevos diseños)Obsoleto (El fabricante ha interrumpido la producción del dispositivo)Activo (Recomendado para nuevos diseños)Activo (Recomendado para nuevos diseños)Obsoleto (El fabricante ha interrumpido la producción del dispositivo)Obsoleto (El fabricante ha interrumpido la producción del dispositivo)
Disponibilidad de muestra del fabricanteNoNoNoNoNoNoNoNoNoNoNoNoNoNo

Embalaje

TMS320C6670ACYP2TMS320C6670ACYPATMS320C6670ACYPA2TMS320C6670AXCYPTMS320C6670AXCYP2TMS320C6670AXCYPATMS320C6670AXCYPA2TMS320C6670CYPTMS320C6670CYP2TMS320C6670CYPATMS320C6670CYPA2TMS320C6670XCPY2TMS320C6670XCYPTMS320C6670XCYPATMS320C6670XCYPA2TMX320C6670AXCYPTMX320C6670CYP
N1234567891011121314151617
Pin841841841841841841841841841841841841841841841841841
Package TypeCYPCYPCYPCYPCYPCYPCYPCYPCYPCYPCYPCYPCYPCYPCYPCYPCYP
Package QTY14414444441
CarrierJEDEC TRAY (5+1)JEDEC TRAY (5+1)JEDEC TRAY (5+1)
Device Marking@2010 TITMS320C6670CYP@2010 TI@2010 TI1.2GHZTMS320C6670XCYPTMS320C6670XCYPTMS320C6670CYP@2010 TIA1GHZTMS320C6670CYPTMS320C6670XCYPTMS320C6670XCYPA1.2GHZ
Width (mm)2424242424242424242424242424242424
Length (mm)2424242424242424242424242424242424
Thickness (mm)2.822.822.822.822.822.822.822.822.822.822.822.822.822.822.822.822.82
Mechanical DataDescargarDescargarDescargarDescargarDescargarDescargarDescargarDescargarDescargarDescargarDescargarDescargarDescargarDescargarDescargarDescargarDescargar

Paramétricos

Parameters / ModelsTMS320C6670ACYP2
TMS320C6670ACYP2
TMS320C6670ACYPA
TMS320C6670ACYPA
TMS320C6670ACYPA2
TMS320C6670ACYPA2
TMS320C6670AXCYP
TMS320C6670AXCYP
TMS320C6670AXCYP2
TMS320C6670AXCYP2
TMS320C6670AXCYPA
TMS320C6670AXCYPA
TMS320C6670AXCYPA2
TMS320C6670AXCYPA2
TMS320C6670CYP
TMS320C6670CYP
TMS320C6670CYP2
TMS320C6670CYP2
TMS320C6670CYPA
TMS320C6670CYPA
TMS320C6670CYPA2
TMS320C6670CYPA2
TMS320C6670XCPY2
TMS320C6670XCPY2
TMS320C6670XCYP
TMS320C6670XCYP
TMS320C6670XCYPA
TMS320C6670XCYPA
TMS320C6670XCYPA2
TMS320C6670XCYPA2
TMX320C6670AXCYP
TMX320C6670AXCYP
TMX320C6670CYP
TMX320C6670CYP
ApplicationsCommunications and TelecomCommunications and TelecomCommunications and TelecomCommunications and TelecomCommunications and TelecomCommunications and TelecomCommunications and TelecomCommunications and TelecomCommunications and TelecomCommunications and TelecomCommunications and TelecomCommunications and TelecomCommunications and TelecomCommunications and TelecomCommunications and TelecomCommunications and TelecomCommunications and Telecom
Approx. Price (US$)168.00 | 1ku168.00 | 1ku168.00 | 1ku168.00 | 1ku168.00 | 1ku
DRAMDDR3DDR3DDR3DDR3DDR3DDR3DDR3DDR3DDR3DDR3DDR3DDR3DDR3DDR3DDR3DDR3DDR3
DSP4 C66x4 C66x4 C66x4 C66x4 C66x4 C66x4 C66x4 C66x4 C66x4 C66x4 C66x4 C66x4 C66x4 C66x4 C66x4 C66x4 C66x
DSP MHz, Max.1000,12001000,12001000,12001000,12001000,12001000,12001000,12001000,12001000,12001000,12001000,12001000,1200
DSP MHz (Max.)1000
1200
1000
1200
1000
1200
1000
1200
1000
1200
EMAC10/100/100010/100/100010/100/100010/100/100010/100/100010/100/100010/100/100010/100/100010/100/100010/100/100010/100/100010/100/100010/100/100010/100/100010/100/100010/100/100010/100/1000
GFLOPS64,76.864,76.864,76.864,76.864,76.864,76.864,76.864
76.8
64
76.8
64,76.864,76.864
76.8
64,76.864,76.864,76.864
76.8
64
76.8
Hardware AcceleratorsVCP2,TCP3d,TCP3e,FFT CoprocessorVCP2,TCP3d,TCP3e,FFT CoprocessorVCP2,TCP3d,TCP3e,FFT CoprocessorVCP2,TCP3d,TCP3e,FFT CoprocessorVCP2,TCP3d,TCP3e,FFT CoprocessorVCP2,TCP3d,TCP3e,FFT CoprocessorVCP2,TCP3d,TCP3e,FFT CoprocessorVCP2
TCP3d
TCP3e
FFT Coprocessor
VCP2
TCP3d
TCP3e
FFT Coprocessor
VCP2,TCP3d,TCP3e,FFT CoprocessorVCP2,TCP3d,TCP3e,FFT CoprocessorVCP2
TCP3d
TCP3e
FFT Coprocessor
VCP2,TCP3d,TCP3e,FFT CoprocessorVCP2,TCP3d,TCP3e,FFT CoprocessorVCP2,TCP3d,TCP3e,FFT CoprocessorVCP2
TCP3d
TCP3e
FFT Coprocessor
VCP2
TCP3d
TCP3e
FFT Coprocessor
On-Chip L2 Cache4096 KB4096 KB4096 KB4096 KB4096 KB4096 KB4096 KB4096 KB4096 KB4096 KB4096 KB4096 KB4096 KB4096 KB4096 KB4096 KB4096 KB
Operating Temperature Range, C-40 to 100,0 to 85-40 to 100,0 to 85-40 to 100,0 to 85-40 to 100,0 to 85-40 to 100,0 to 85-40 to 100,0 to 85-40 to 100,0 to 85-40 to 100,0 to 85-40 to 100,0 to 85-40 to 100,0 to 85-40 to 100,0 to 85-40 to 100,0 to 85
Operating Temperature Range(C)-40 to 100
0 to 85
-40 to 100
0 to 85
-40 to 100
0 to 85
-40 to 100
0 to 85
-40 to 100
0 to 85
Other On-Chip Memory2048 KB2048 KB2048 KB2048 KB2048 KB2048 KB2048 KB2048 KB2048 KB2048 KB2048 KB2048 KB2048 KB2048 KB2048 KB2048 KB2048 KB
PCI/PCIe2 PCIe Gen22 PCIe Gen22 PCIe Gen22 PCIe Gen22 PCIe Gen22 PCIe Gen22 PCIe Gen22 PCIe Gen22 PCIe Gen22 PCIe Gen22 PCIe Gen22 PCIe Gen22 PCIe Gen22 PCIe Gen22 PCIe Gen22 PCIe Gen22 PCIe Gen2
Package Size: mm2:W x L, PKGSee datasheet (FCBGA)See datasheet (FCBGA)See datasheet (FCBGA)See datasheet (FCBGA)See datasheet (FCBGA)See datasheet (FCBGA)See datasheet (FCBGA)See datasheet (FCBGA)See datasheet (FCBGA)See datasheet (FCBGA)See datasheet (FCBGA)See datasheet (FCBGA)
Package Size: mm2:W x L (PKG)See datasheet (FCBGA)See datasheet (FCBGA)See datasheet (FCBGA)See datasheet (FCBGA)See datasheet (FCBGA)
RatingCatalogCatalogCatalogCatalogCatalogCatalogCatalogCatalogCatalogCatalogCatalogCatalogCatalogCatalogCatalogCatalogCatalog
Serial I/OAIF2,I2C,RapidIO,SPI,UARTAIF2,I2C,RapidIO,SPI,UARTAIF2,I2C,RapidIO,SPI,UARTAIF2,I2C,RapidIO,SPI,UARTAIF2,I2C,RapidIO,SPI,UARTAIF2,I2C,RapidIO,SPI,UARTAIF2,I2C,RapidIO,SPI,UARTAIF2
I2C
RapidIO
SPI
UART
AIF2
I2C
RapidIO
SPI
UART
AIF2,I2C,RapidIO,SPI,UARTAIF2,I2C,RapidIO,SPI,UARTAIF2
I2C
RapidIO
SPI
UART
AIF2,I2C,RapidIO,SPI,UARTAIF2,I2C,RapidIO,SPI,UARTAIF2,I2C,RapidIO,SPI,UARTAIF2
I2C
RapidIO
SPI
UART
AIF2
I2C
RapidIO
SPI
UART
Serial RapidIO1 (four lanes)1 (four lanes)1 (four lanes)1 (four lanes)1 (four lanes)1 (four lanes)1 (four lanes)1 (four lanes)1 (four lanes)1 (four lanes)1 (four lanes)1 (four lanes)1 (four lanes)1 (four lanes)1 (four lanes)1 (four lanes)1 (four lanes)
Total On-Chip Memory, KB652865286528652865286528652865286528652865286528
Total On-Chip Memory (KB)65286528652865286528

Plan ecológico

TMS320C6670ACYP2TMS320C6670ACYPATMS320C6670ACYPA2TMS320C6670AXCYPTMS320C6670AXCYP2TMS320C6670AXCYPATMS320C6670AXCYPA2TMS320C6670CYPTMS320C6670CYP2TMS320C6670CYPATMS320C6670CYPA2TMS320C6670XCPY2TMS320C6670XCYPTMS320C6670XCYPATMS320C6670XCYPA2TMX320C6670AXCYPTMX320C6670CYP
RoHSObedienteObedienteObedienteObedienteObedienteObedienteObedienteDesobedienteDesobedienteDesobedienteObedienteDesobedienteObedienteObedienteObedienteDesobedienteDesobediente
Pb gratisNoNoNoNoNo

Notas de aplicación

  • AIF1-to-AIF2 Antenna Interface Migration Guide for KeyStone Devices
    PDF, 640 Kb, Archivo publicado: nov 9, 2010
  • Connecting AIF to FFTC Guide for KeyStone Devices
    PDF, 441 Kb, Archivo publicado: nov 9, 2010
  • Keystone NDK FAQ
    PDF, 54 Kb, Archivo publicado: oct 3, 2016
    This document is a collection of frequently asked questions (FAQ) on running the NDK examples on the KeyStoneв„ў family of devices.
  • TI Keystone DSP Hyperlink SerDes IBIS-AMI Models
    PDF, 3.2 Mb, Archivo publicado: oct 9, 2014
    This document describes the organization, structure, and proper usage of the TI serializer and deserializer (SerDes) IBIS-AMI models for Keystone DSP Hyperlink interface.
  • TI Keystone DSP PCIe SerDes IBIS-AMI Models
    PDF, 4.8 Mb, Archivo publicado: oct 9, 2014
    This document describes the organization, structure, and proper usage of the TI serializer and deserializer (SerDes) IBIS-AMI models for Keystone DSP PCIe interface.
  • SerDes Implementation Guidelines for KeyStone I Devices
    PDF, 590 Kb, Archivo publicado: oct 31, 2012
    The goal of KeyStone I SerDes collateral material is to make system implementation easier for the customer by providing the system solution. For these SerDes-based interfaces, it is not assumed that the system designer is familiar with the industry specifications, SerDes technology, or RF/microwave PCB design. However, it is still expected that the PCB design work will be supervised by a knowledge
  • KeyStone I DDR3 Initialization (Rev. E)
    PDF, 114 Kb, Revisión: E, Archivo publicado: oct 28, 2016
    The initialization of the DDR3 DRAM controller on KeyStone I DSPs is straightforward as long as the proper steps are followed. However, if some steps are omitted or if some sequence-sensitive steps are implemented in the wrong order, DDR3 operation will be unpredictable.All DDR3 initialization routines must contain the basic register writes to configure the memory controller within the DSP
  • TMS320C66x DSP Generation of Devices (Rev. A)
    PDF, 245 Kb, Revisión: A, Archivo publicado: abr 25, 2011
  • Hardware Design Guide for KeyStone Devices (Rev. C)
    PDF, 1.7 Mb, Revisión: C, Archivo publicado: sept 15, 2013
  • Tuning VCP2 and TCP2 Bit Error Rate Performance
    PDF, 293 Kb, Archivo publicado: feb 11, 2011
    In most customer applications, a high level of decoding bit error rate (BER) performance is required. Since Convolutional codes and Turbo codes are widely used in wireless communication systems, TI DSPs integrate two high-performance embedded coprocessors (enhanced Viterbi decoder coprocessor and enhanced Turbo decoder coprocessor) that significantly speed up channel-decoding operations on-chip.
  • SERDES Link Commissioning on KeyStone I and II Devices
    PDF, 138 Kb, Archivo publicado: abr 13, 2016
    The serializer-deserializer (SerDes) performs serial-to-parallel conversions on data received from a peripheral device and parallel-to-serial conversion on data received from the CPU. This application report explains the SerDes transmit and receive parameters tuning, tools and some debug techniques for TI Keystone I and Keystone II devices.
  • PCIe Use Cases for KeyStone Devices
    PDF, 320 Kb, Archivo publicado: dic 13, 2011
  • The C6000 Embedded Application Binary Interface Migration Guide (Rev. A)
    PDF, 20 Kb, Revisión: A, Archivo publicado: nov 10, 2010
    The C6000 compiler tools support a new ELF-based ABI named EABI. Prior to this time, the compiler only supported a single ABI, which is now named COFF ABI. The following compelling best-in-class features are available under the C6000 EABI:GeneralZero-init globals: “int gvar;” gets set to 0 before main runs.Dynamic linking: Add code to a running system.Native ROM
  • Optimizing Loops on the C66x DSP
    PDF, 585 Kb, Archivo publicado: nov 9, 2010
  • Clocking Design Guide for KeyStone Devices
    PDF, 1.5 Mb, Archivo publicado: nov 9, 2010
  • DDR3 Design Requirements for KeyStone Devices (Rev. B)
    PDF, 582 Kb, Revisión: B, Archivo publicado: jun 5, 2014
  • Multicore Programming Guide (Rev. B)
    PDF, 1.8 Mb, Revisión: B, Archivo publicado: agosto 29, 2012
    As application complexity continues to grow, we have reached a limit on increasing performance by merely scaling clock speed. To meet the ever-increasing processing demand, modern System-On-Chip solutions contain multiple processing cores. The dilemma is how to map applications to multicore devices. In this paper, we present a programming methodology for converting applications to run on multicore
  • Thermal Design Guide for DSP and ARM Application Processors (Rev. A)
    PDF, 324 Kb, Revisión: A, Archivo publicado: agosto 17, 2016
    This application report has been compiled to provide specific information and considerations regarding thermal design requirements for all DSP and ARM-based single and multi-core processors (collectively referred to as “processors”, “System-on-chip”, or “SoC”). The information contained within this document is intended to provide a minimum level of understanding with regards to the thermal require

Linea modelo

Clasificación del fabricante

  • Semiconductors> Processors> Digital Signal Processors> C6000 DSP> C66x DSP