Datasheet Texas Instruments TMS320C6671 — Ficha de datos

FabricanteTexas Instruments
SerieTMS320C6671
Datasheet Texas Instruments TMS320C6671

Procesador de señal digital de punto fijo y flotante

Hojas de datos

TMS320C6671 Fixed and Floating-Point Digital Signal Processor datasheet
PDF, 2.1 Mb, Revisión: E, Archivo publicado: mayo 7, 2014
Extracto del documento

Precios

Estado

TMS320C6671ACYPTMS320C6671ACYP25TMS320C6671ACYPATMS320C6671ACYPA25
Estado del ciclo de vidaActivo (Recomendado para nuevos diseños)Activo (Recomendado para nuevos diseños)Activo (Recomendado para nuevos diseños)Activo (Recomendado para nuevos diseños)
Disponibilidad de muestra del fabricanteNoNo

Embalaje

TMS320C6671ACYPTMS320C6671ACYP25TMS320C6671ACYPATMS320C6671ACYPA25
N1234
Pin841841841841
Package TypeCYPCYPCYPCYP
Package QTY44444444
CarrierJEDEC TRAY (5+1)
Device MarkingTMS320C6671CYP1.25GHZTMS320C6671CYPA1.25GHZ
Width (mm)24242424
Length (mm)24242424
Thickness (mm)2.822.822.822.82
Mechanical DataDescargarDescargarDescargarDescargar

Paramétricos

Parameters / ModelsTMS320C6671ACYP
TMS320C6671ACYP
TMS320C6671ACYP25
TMS320C6671ACYP25
TMS320C6671ACYPA
TMS320C6671ACYPA
TMS320C6671ACYPA25
TMS320C6671ACYPA25
ApplicationsCommunications and TelecomCommunications and TelecomCommunications and TelecomCommunications and Telecom
DRAMDDR3DDR3DDR3DDR3
DSP1 C66x1 C66x1 C66x1 C66x
DSP MHz, Max.1000,12501000,12501000,12501000,1250
EMAC2-Port 1Gb Switch2-Port 1Gb Switch2-Port 1Gb Switch2-Port 1Gb Switch
GFLOPS16,2016,2016,2016,20
On-Chip L2 Cache512 KB512 KB512 KB512 KB
Operating Temperature Range, C-40 to 100,0 to 85-40 to 100,0 to 85-40 to 100,0 to 85-40 to 100,0 to 85
Other On-Chip Memory4096 KB4096 KB4096 KB4096 KB
PCI/PCIe2 PCIe Gen22 PCIe Gen22 PCIe Gen22 PCIe Gen2
Package Size: mm2:W x L, PKGSee datasheet (FCBGA)See datasheet (FCBGA)See datasheet (FCBGA)See datasheet (FCBGA)
RatingCatalogCatalogCatalogCatalog
Serial I/OI2C,RapidIO,SPI,TSIP,UARTI2C,RapidIO,SPI,TSIP,UARTI2C,RapidIO,SPI,TSIP,UARTI2C,RapidIO,SPI,TSIP,UART
Serial RapidIO1 (four lanes)1 (four lanes)1 (four lanes)1 (four lanes)
Total On-Chip Memory, KB4800480048004800

Plan ecológico

TMS320C6671ACYPTMS320C6671ACYP25TMS320C6671ACYPATMS320C6671ACYPA25
RoHSObedienteObedienteObedienteObediente

Notas de aplicación

  • TI Keystone DSP Hyperlink SerDes IBIS-AMI Models
    PDF, 3.2 Mb, Archivo publicado: oct 9, 2014
    This document describes the organization, structure, and proper usage of the TI serializer and deserializer (SerDes) IBIS-AMI models for Keystone DSP Hyperlink interface.
  • TI Keystone DSP PCIe SerDes IBIS-AMI Models
    PDF, 4.8 Mb, Archivo publicado: oct 9, 2014
    This document describes the organization, structure, and proper usage of the TI serializer and deserializer (SerDes) IBIS-AMI models for Keystone DSP PCIe interface.
  • SerDes Implementation Guidelines for KeyStone I Devices
    PDF, 590 Kb, Archivo publicado: oct 31, 2012
    The goal of KeyStone I SerDes collateral material is to make system implementation easier for the customer by providing the system solution. For these SerDes-based interfaces, it is not assumed that the system designer is familiar with the industry specifications, SerDes technology, or RF/microwave PCB design. However, it is still expected that the PCB design work will be supervised by a knowledge
  • KeyStone I DDR3 Initialization (Rev. E)
    PDF, 114 Kb, Revisión: E, Archivo publicado: oct 28, 2016
    The initialization of the DDR3 DRAM controller on KeyStone I DSPs is straightforward as long as the proper steps are followed. However, if some steps are omitted or if some sequence-sensitive steps are implemented in the wrong order, DDR3 operation will be unpredictable.All DDR3 initialization routines must contain the basic register writes to configure the memory controller within the DSP
  • TMS320C66x DSP Generation of Devices (Rev. A)
    PDF, 245 Kb, Revisión: A, Archivo publicado: abr 25, 2011
  • Hardware Design Guide for KeyStone Devices (Rev. C)
    PDF, 1.7 Mb, Revisión: C, Archivo publicado: sept 15, 2013
  • SERDES Link Commissioning on KeyStone I and II Devices
    PDF, 138 Kb, Archivo publicado: abr 13, 2016
    The serializer-deserializer (SerDes) performs serial-to-parallel conversions on data received from a peripheral device and parallel-to-serial conversion on data received from the CPU. This application report explains the SerDes transmit and receive parameters tuning, tools and some debug techniques for TI Keystone I and Keystone II devices.
  • PCIe Use Cases for KeyStone Devices
    PDF, 320 Kb, Archivo publicado: dic 13, 2011
  • Clocking Design Guide for KeyStone Devices
    PDF, 1.5 Mb, Archivo publicado: nov 9, 2010
  • The C6000 Embedded Application Binary Interface Migration Guide (Rev. A)
    PDF, 20 Kb, Revisión: A, Archivo publicado: nov 10, 2010
    The C6000 compiler tools support a new ELF-based ABI named EABI. Prior to this time, the compiler only supported a single ABI, which is now named COFF ABI. The following compelling best-in-class features are available under the C6000 EABI:GeneralZero-init globals: “int gvar;” gets set to 0 before main runs.Dynamic linking: Add code to a running system.Native ROM
  • Optimizing Loops on the C66x DSP
    PDF, 585 Kb, Archivo publicado: nov 9, 2010
  • DDR3 Design Requirements for KeyStone Devices (Rev. B)
    PDF, 582 Kb, Revisión: B, Archivo publicado: jun 5, 2014
  • Multicore Programming Guide (Rev. B)
    PDF, 1.8 Mb, Revisión: B, Archivo publicado: agosto 29, 2012
    As application complexity continues to grow, we have reached a limit on increasing performance by merely scaling clock speed. To meet the ever-increasing processing demand, modern System-On-Chip solutions contain multiple processing cores. The dilemma is how to map applications to multicore devices. In this paper, we present a programming methodology for converting applications to run on multicore
  • Thermal Design Guide for DSP and ARM Application Processors (Rev. A)
    PDF, 324 Kb, Revisión: A, Archivo publicado: agosto 17, 2016
    This application report has been compiled to provide specific information and considerations regarding thermal design requirements for all DSP and ARM-based single and multi-core processors (collectively referred to as “processors”, “System-on-chip”, or “SoC”). The information contained within this document is intended to provide a minimum level of understanding with regards to the thermal require

Linea modelo

Clasificación del fabricante

  • Semiconductors> Processors> Digital Signal Processors> C6000 DSP> C66x DSP