Datasheet Analog Devices AD827JCHIPS — Ficha de datos

REVISIONS
LTR DESCRIPTION A DATE (YR-MO-DA) APPROVED 93-04-04 M. A. FRYE 94-05-25 M. A. FRYE Sheet 3: Paragraph 1.3, Input common mode voltage range (VCM),
delete “VS” and substitute “±VS”.
Sheet 5: Table I, Quiescent power supply current test, IQ, conditions column,
delete “VS = ±5.0 V” and substitute “VS = ±5.0 V, VOUT = 0 V” and
delete “VS = ±15.0 V” and substitute “VS = ±15.0 V, VOUT = 0 V”.
Sheet 8: Table I, Settling time test, tS, delete subgroup “9” and substitute
subgroup “4”. Table I, Overshoot test, OS, delete subgroup “9” and substitute
subgroup “4”. Rise time test, tR, delete subgroups “9, 10, 11” and substitute
subgroups “4, 5, 6”. Fall time test, tF, delete subgroups “9, 10, 11” and
substitute subgroups “4, 5, 6”. Delete footnote “1/” and substitute
“1/ Unless otherwise specified, for dc tests, source resistance (RS) < 100 Ω,
load resistance (RL) > 100 kΩ, and VOUT = 0 V”.
Sheet 11: Table IIA, group A test requirements, delete “9, 10, 11 (five times).
Group B endpoint electrical parameters, delete “9, 10, 11” (two times).
Changes in accordance with N.O.R. 5962-R077-93.
Sheet 7: Table I. Slew rate test. Under the “Test” column, delete footnote “7/” B entirely. With the symbol of “SR-“ and the condition of “VS = ±15 V”, delete the
group A subgroup 4 value of “200 V/µs” and substitute “180 V/µs”.
Full power bandwidth test. Under the “Test column, footnote “8/” will be
renumbered as footnote “7/”.
Sheet 8: Table I. Delete footnote “7/” entirely. Rise time test. Under the
“Test” column, footnote “9/” will be renumbered as footnote “8/”.
Fall time test. Under the “Test” column, footnote “9/” will be renumbered as …

a
FEATURES
High Speed
50 MHz Unity Gain Stable Operation
300 V/ms Slew Rate
120 ns Settling Time
Drives Unlimited Capacitive Loads
Excellent Video Performance
0.04% Differential Gain @ 4.4 MHz
0.198 Differential Phase @ 4.4 MHz
Good DC Performance
2 mV max Input Offset Voltage
15 mV/8C Input Offset Voltage Drift
Available in Tape and Reel in Accordance with
EIA-481A Standard
Low Power
Only 10 mA Total Supply Current for Both Amplifiers
ⴞ5 V to ⴞ15 V Supplies High Speed, Low Power
Dual Op Amp
AD827
CONNECTION DIAGRAMS
8-Lead Plastic (N) and Cerdip
(Q) Packages 16-Lead Small Outline …

a
FEATURES
High Speed
50 MHz Unity Gain Stable Operation
300 V/ms Slew Rate
120 ns Settling Time
Drives Unlimited Capacitive Loads
Excellent Video Performance
0.04% Differential Gain @ 4.4 MHz
0.198 Differential Phase @ 4.4 MHz
Good DC Performance
2 mV max Input Offset Voltage
15 mV/8C Input Offset Voltage Drift
Available in Tape and Reel in Accordance with
EIA-481A Standard
Low Power
Only 10 mA Total Supply Current for Both Amplifiers
ⴞ5 V to ⴞ15 V Supplies High Speed, Low Power
Dual Op Amp
AD827
CONNECTION DIAGRAMS
8-Lead Plastic (N) and Cerdip
(Q) Packages 16-Lead Small Outline …