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  High Performance Switch Mode Power Solutions for Altera Low Voltage FPGAs &mdash Design Solutions 43
  PDF, 158 Kb, Archivo publicado: jun 1, 2004
  Extracto del documento

  Design Solutions 43
  June 2004
  High Performance Switch Mode Power Solutions
  for Altera Low Voltage FPGAs
  by Mike Shriver
  INTRODUCTION
  The core voltages for FPGAs are moving lower as a result
  of advances in the fabrication process. The newest FPGA
  family from Altera, the StratixВ® II, now requires a core
  voltage of 1.2V and the Stratix, Stratix GX, HardCopyВ®
  Stratix and CycloneTM families require a core voltage of
  1.5V. This article discusses how to power the core and I/O
  of low voltage FPGAs using the latest step-down switch
  mode controllers from Linear Technology Corporation.
  To ensure correct selection of power management circuitry,
  it is recommended to use Altera’s PowerPlay Power Estimation Tools to obtain accurate results. Tools are available
  to help determine power consumption before and during
  the design process. More information on these tools is
  available from Altera’s website: http://www.altera.com/
  support/devices/estimator/pow-powerplay.html.
  Overview
  The load and input voltage requirements for FPGA systems vary considerably. A single FPGA typically requires
  less than 2A, but for systems using multiple FPGAs, the …

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  Wide Input Range, High Efficiency DDR Termination Power Supply Achieves Fast Transient Response &mdash DN281
  PDF, 84 Kb, Archivo publicado: abr 1, 2002
  Extracto del documento

  advertisement Wide Input Range, High Efficiency DDR Termination Power
  Supply Achieves Fast Transient Response – Design Note 281
  Wei Chen
  Introduction
  Today’s complicated computing and communication
  systems demand high system memory bandwidths. The
  emerging standard is Double Data Rate (DDR) memory
  because of its higher data rate and relatively low cost.
  A typical DDR memory system needs at least two main
  power supplies: VDD for the I/O power and V TT for the
  termination power. To ensure good signal quality and
  fast data rate, the termination power supply (V TT ) must
  always track the VDD with V TT = VDD/2. V TT can be as
  low as 0.6V. Since the termination resistors can carry
  current in either direction, the V TT power supply must
  be able to both source and sink current while tracking
  the VDD supply. A family of new termination/tracking
  controllers, including the LTC В®3717, LTC3718 and
  LTC3831, satisfy these DDR requirements. on-time programmed by the input voltage and output
  voltage. This scheme allows a fairly constant switching
  frequency while achieving an extremely fast load transient response. In addition, the controller’s minimum
  on-time is less than 100ns, allowing for a very small
  duty cycle at a very high switching frequency, thus …

Artículos

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  High Efficiency DDR Termination Power Supplies Source and Sink More than 10 Amps &mdash LT Journal
  PDF, 205 Kb, Archivo publicado: marzo 1, 2002
  Extracto del documento

  DESIGN FEATURES High Efficiency DDR Termination
  Power Supplies Source and Sink
  More than 10 Amps
  by Wei Chen
  Introduction
  The emerging standard for system
  memory in computing and communication systems is Double Data Rate
  (DDR) memory. Typical DDR memory
  needs at least two main power supplies: VDD and VTT, where VDD powers
  the I/O, and VTT powers the I/O termination. To ensure good signal
  quality and fast data rate, the termination power supply VTT must always
  track the VDD supply with VTT = VDD/
  2. Since the termination resistors can
  carry current in either direction, the
  VTT power supply must be able to
  both source and sink current while
  tracking the VDD supply. A typical
  DDR termination power supply for a
  PC application requires 2A to 10A of
  current. In servers, high power workstations or broadband networking
  equipment applications, the DDR termination supply current may well
  exceed 10A. At these current levels, a
  linear regulator is not a viable solu-VDD …

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• Power Management > Switching Regulator > DDR Memory/Bus Termination