Datasheet Analog Devices AD9248BCPZRL-40 — Ficha de datos

14-Bit, 20 MSPS/40 MSPS/65 MSPS
Dual A/D Converter
AD9248
FUNCTIONAL BLOCK DIAGRAM FEATURES AVDD AGND
OTR_A VIN+_A 14
SHA 14 ADC OUTPUT
MUX/
BUFFERS VIN–_A REFT_A
CLOCK
DUTY CYCLE
STABILIZER VREF GENERAL DESCRIPTION
The AD9248 is a dual, 3 V, 14-bit, 20 MSPS/40 MSPS/65 MSPS
analog-to-digital converter (ADC). It features dual high
performance sample-and hold amplifiers (SHAs) and an
integrated voltage reference. The AD9248 uses a multistage
differential pipelined architecture with output error correction
logic to provide 14-bit accuracy and to guarantee no missing
codes over the full operating temperature range at up to
65 MSPS data rates. The wide bandwidth, differential SHA
allows for a variety of user-selectable input ranges and offsets,
including single-ended applications. It is suitable for various
applications, including multiplexed systems that switch fullscale voltage levels in successive channels and for sampling
inputs at frequencies well beyond the Nyquist rate. …

14-Bit, 40 MSPS
Dual Analog-to-Digital Converter
ADW12001
FEATURES FUNCTIONAL BLOCK DIAGRAM
AVDD VIN+_A GENERAL DESCRIPTION
The ADW12001 is a dual, 3 V, 14-bit, 40 MSPS analog-todigital converter (ADC). It features dual high performance
sample-and-hold amplifiers (SHAs) and an integrated voltage
reference. The ADW12001 uses a multistage differential
pipelined architecture with output error correction logic to
provide 14-bit accuracy and to guarantee no missing codes
over the full operating temperature. The wide bandwidth
differential SHA allows for a variety of user-selectable input
ranges and offsets, including single-ended applications. It is
suitable for various applications, including multiplexed systems
that switch full-scale voltage levels in successive channels and
for sampling inputs at frequencies well beyond the Nyquist rate.
Dual single-ended clock inputs are used to control all internal
conversion cycles. A duty cycle stabilizer is available and can
compensate for wide variations in the clock duty cycle, allowing
the converter to maintain excellent performance. The digital
output data is presented in either straight binary or twos complement format. Out-of-range signals indicate an overflow
condition, which can be used with the most significant bit to
determine low or high overflow. OTR_A …