Datasheet Intersil KAD5610P-25Q72 — Ficha de datos

DATASHEET
KAD5610P FN6810
Rev 3.00
May 31, 2016 Dual 10-Bit, 250/210/170/125MSPS A/D Converter
The KAD5610P is a family of low-power, high performance,
dual-channel 10-bit, analog-to-digital converters. Designed
with Intersil’s proprietary FemtoCharge™ technology on a
standard CMOS process, the family supports sampling rates of
up to 250MSPS. The KAD5610P-25 is the fastest member of
this pin-compatible family, which also features sample rates of
210MSPS (KAD5610P-21), 170MSPS (KAD5610P-17) and
125MSPS (KAD5610P-12). Features A Serial Peripheral Interface (SPI) port allows for extensive
configurability, as well as fine control of gain, skew and offset
matching between the two converter cores. Clock phase selection Programmable gain, offset and skew control 1.3GHz analog input bandwidth 60fs clock jitter Over-range indicator Selectable clock divider: à 1, à 2 or à 4 Nap and sleep modes Two’s complement, gray code or binary data format Digital output data is presented in selectable LVDS or CMOS
formats. The KAD5610P is available in a 72 Ld QFN package
with an exposed paddle. Performance is specified over the full
industrial temperature range (-40В°C to +85В°C). DDR LVDS compatible or LVCMOS outputs Programmable built-in test patterns Single-supply 1.8V operation Key Specifications Pb-free (RoHs compliant) SNR = 60.7dBFS for fIN = 105MHz (-1dBFS) Applications SFDR = 86.1dBc for fIN = 105MHz (-1dBFS) Power amplifier linearization Power consumption
-411mW at 250MSPS
-327mW at 125MSPS Radar and satellite antenna array processing Broadband communications High-performance data acquisition Communications test equipment CLKP OVDD CLKDIV AVDD WiMAX and microwave receivers CLKOUTP CLOCK
GENERATION CLKN AINP CLKOUTN 10-BIT
250MSPS
ADC SHA
AINN VREF …