DATASHEET
ISLA112P25M FN7646
Rev 1.00
November 17, 2011 Low Power 12-Bit, 250MSPS ADC
The ISLA112P25MREP is a low-power 12-bit, 250MSPS
analog-to-digital converter. Designed with Intersil’s
proprietary FemtoChargeв„ў technology on a standard
CMOS process. Features A serial peripheral interface (SPI) port allows for
extensive configurability, as well as fine control of
various parameters such as gain and offset. 60fs Clock Jitter Digital output data is presented in selectable LVDS or
CMOS formats. The ISLA112P25MREP is available in a
72 Ld QFN package with an exposed paddle. Operating
from a 1.8V supply, performance is specified over the
full military temperature range (-55°C to +125°C). Clock Phase Selection Programmable Gain, Offset and Skew Control 1.3GHz Analog Input Bandwidth Over-Range Indicator Selectable Clock Divider: 1, 2 or 4 Nap and Sleep Modes Two’s Complement, Gray Code or Binary Data
Format SDR/DDR LVDS-Compatible or LVCMOS Outputs Applications Programmable Built-in Test Patterns Power Amplifier Linearization Single-Supply 1.8V Operation Radar and Satellite Antenna Array Processing Pb-Free (RoHS Compliant) Broadband Communications VID Features High-Performance Data Acquisition Specifications per DSCC VID V62/10609 Communications Test Equipment Full Military Temperature Electrical Performance
from -55В°C to +125В°C Key Specifications Controlled Baseline with One Wafer Fabrication Site
and One Assembly/Test Site SNR = 62.7dBFS for fIN = 105MHz (-1dBFS) SFDR = 67dBc for fIN = 105MHz (-1dBFS) Full Homogeneous Lot Processing in Wafer Fab Total Power Consumption
-310mW @ 250MSPS (SDR Mode)
-234mW @ 250MSPS (DDR Mode) No Combination of Wafer Fabrication Lots in
Assembly Full Traceability Through Assembly and Test by Date/Trace Code Assignment Enhanced Process Change Notification Enhanced Obsolescence Management CLKP OVDD AVDD Block Diagram CLKDIV Eliminates Need for Up-Screening a COTS
Component CLKOUTP CLOCK
GENERATION CLKN CLKOUTN D[11:0]P
12-BIT …
