Datasheet Analog Devices AD652JPZ-REEL7 — Ficha de datos

REVISIONS
LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Table I; for power supply rejection ratio test, change limit from
“0.01 %/V minimum” to “0.01 %/V maximum”.
Changes in accordance with N.O.R. 5962-R011-94. 93-10-18 M. A. FRYE B Drawing updated to reflect current requirements. Redrawn. -ro 02-01-08 R. MONNIN C Make changes to 1.2.4, 1.4, and Table IIA. Add junction temperature and
power dissipation limits under 1.3. Add Table IIB. Under paragraphs 4.2.1 and
4.4.2.1, delete test condition B and substitute test condition D.
Add subgroups 4, 5, 6, 10, and 11 to Table I and Table IIA. -ro 11-02-28 C SAFFLE REV
SHEET
REV
SHEET
REV STATUS REV C C C C C C C C C C C OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 PMIC N/A PREPARED BY
DAN WONNELL STANDARD
MICROCIRCUIT
DRAWING DLA LAND AND MARITIME
COLUMBUS, OHIO 43218-3990
http://www.dscc.dla.mil CHECKED BY
SANDRA ROONEY
APPROVED BY THIS DRAWING IS AVAILABLE
FOR USE BY ALL
DEPARTMENTS
AND AGENCIES OF THE
DEPARTMENT OF DEFENSE AMSC N/A MICHAEL A. FRYE
DRAWING APPROVAL DATE …

Monolithic Synchronous
Voltage-to-Frequency Converter
AD652
The AD652 is available in five performance grades. The 20-lead
PLCC-packaged JP and KP grades are specified for operation
over the 0°C to +70°C commercial temperature range. The
16-lead CERDIP-packaged AQ and BQ grades are specified for
operation over the −40°C to +85°C industrial temperature
range. The AD652SQ is available for operation over the full
−55°C to +125°C extended temperature range. FEATURES
Full-scale frequency (up to 2 MHz) set by external system
clock
Extremely low linearity error (0.005% max at 1 MHz FS,
0.02% max at 2 MHz FS)
No critical external components required
Accurate 5 V reference voltage
Low drift (25 ppm/°C max)
Dual-or single-supply operation
Voltage or current input
MIL-STD-883 compliant versions available PRODUCT HIGHLIGHTS
1. The use of an external clock to set the full-scale frequency
allows the AD652 to achieve linearity and stability far
superior to other monolithic VFCs. By using the same clock …