Plastic Packages for Integrated Circuits
Thin Shrink Small Outline Exposed Pad Plastic Packages (EPTSSOP)
M24.173B
24 LEAD THIN SHRINK SMALL OUTLINE EXPOSED PAD
PLASTIC PACKAGE N
INDEX
AREA E 0.25(0.010) M 2 A
L 0.05(0.002)
-A-A D О±
A2
c e A1 b
0.10(0.004) M 0.25
0.010 SEATING PLANE -C-2 SYMBOL 3
TOP VIEW 1 INCHES GAUGE
PLANE -B1 B M E1 0.10(0.004)
C A M MIN 3 NOTES 0.047 -1.20 -0.006 0.00 0.15 -A2 0.031 0.051 0.80 1.05 -b 0.0075 0.0118 0.19 0.30 9 c 0.0035 0.0079 0.09 0.20 -D 0.303 0.311 7.70 7.90 3 E1 0.169 0.177 4.30 4.50 4 0.026 BSC 0.65 BSC -E 0.246 0.256 6.25 6.50 -L 0.0177 0.0295 0.45 0.75 6 О± 0o 8o 0o 8o -P -0.197 -5.00 11 P1 -0.126 -3.20 NOTES: P1 MAX 0.000 e -MIN A1 N B S MILLIMETERS MAX 24 24 7 11
Rev. 1 11/03 1. These package dimensions are within allowable dimensions of
JEDEC MO-153-ADT, Issue F.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.15mm (0.006 inch) per side.
4. Dimension “E1” does not include interlead flash or protrusions. …
