DATASHEET
CD4043BMS, CD4044BMS FN3311
Rev 0.00
December 1992 CMOS Quad 3 State R/S Latches Features Pinout High Voltage Types (20V Rating) CD4043BMS
TOP VIEW Quad NOR R/S Latch-CD4043BMS Quad NAND R/S Latch -CD4044BMS 3 State Outputs with Common Output ENABLE Separate SET and RESET Inputs for Each Latch NOR and NAND Configuration 5V, 10V and 15V Parametric Ratings Standardized Symmetrical Output Characteristics 100% Tested for Quiescent Current at 20V Maximum Input Current of 1пЃa at 18V Over Full Package-Temperature Range;
-100nA at 18V and 25oC Noise Margin (Over Full Package Temperature Range):
-1V at VDD = 5V
-2V at VDD = 10V
-2.5V at VDD = 15V Meets All Requirements of JEDEC Tentative Standard
No. 13B, “Standard Specifications for Description of �B’
Series CMOS Devices” Q4 1 16 VDD Q1 2 15 R4 R1 3 14 S4 S1 4 13 NC ENABLE 5 12 S3 S2 6 11 R3 R2 7 10 Q3 VSS 8 9 Q2 NC = NO CONNECTION CD4044BMS
TOP VIEW Q4 1 16 VDD NC 2 15 S4 Applications S1 3 14 R4 Holding Register in Multi-Register System R1 4 13 Q1 ENABLE 5 12 R3 Four Bits of Independent Storage with Output ENABLE Strobed Register General Digital Logic CD4043BMS for Positive Logic Systems CD4044BMS for Negative Logic Systems 6 11 S3 S2 7 10 Q3 R2 VSS 8 9 Q2 NC = NO CONNECTION Description
CD4043BMS types are quad cross-coupled 3-state CMOS NOR
latches and the CD4044BMS types are quad cross-coupled 3state CMOS NAND latches. Each latch has a separate Q output
and individual SET and RESET inputs. The Q outputs are controlled by a common ENABLE input. A logic “1” or high on the
ENABLE input connects the latch states to the Q outputs. A logic
“0” or low on the ENABLE input disconnects the latch states from
the Q outputs, results in an open circuit feature allows common
busing of the outputs.
The CD4043BMS and CD4044BMS are supplied in these 16lead outline packages:
Braze Seal DIP
Frit Seal DIP
Ceramic Flatpack …
