DATASHEET
CD4011BMS, CD4012BMS, CD4023BMS FN3079
Rev 0.00
November 1994 CMOS NAND Gates Features Pinouts High-Voltage Types (20V Rating) CD4011BMS
TOP VIEW Propagation Delay Time = 60ns (typ.) at CL = 50pF,
VDD = 10V Buffered Inputs and Outputs Standardized Symmetrical Output Characteristics Maximum Input Current of 1пЃA at 18V Over Full PackageTemperature Range; 100nA at 18V and +25oC 100% Tested for Maximum Quiescent Current at 20V 5V, 10V and 15V Parametric Ratings A 1 14 VDD B 2 13 H J = AB 3 12 G K = CD 4 11 M = GH C 5 10 L = EF D 6 9 E VSS 7 8 F Noise Margin (Over Full Package Temperature Range):
-1V at VDD = 5V
-2V at VDD = 10V
-2.5V at VDD = 15V Meets All Requirements of JEDEC Tentative Standards
No. 13B, “Standard Specifications for Description of
“B” Series CMOS Device’s Description
CD4011BMS -Quad 2 Input CD4012BMS
TOP VIEW 14 VDD J = ABCD 1
A 2 13 K = EFGH B 3 12 H C 4 11 G D 5 10 F CD4012BMS -Dual 4 Input NC 6 9 E CD4023BMS -Triple 3 Input VSS 7 CD4011BMS, CD4012BMS, and CD4023BMS NAND gates
provide the system designer with direct implementation of
the NAND function and supplement the existing family of
CMOS gates. All inputs and outputs are buffered.
The CD4011BMS, CD4012BMS and the CD4023BMS is
supplied in these 14 lead outline packages: 8 NC
NC = NO CONNECTION CD4023BMS
TOP VIEW A 1 14 VDD B 2 13 G CD4011B CD4012B CD4023B D 3 12 H Braze Seal DIP H4Q H4H H4Q E 4 11 I Frit Seal DIP H1B H1B H1B F 5 10 L = GHI Ceramic Flatpack H3W H3W H3W K = DEF 6
VSS 7 FN3079 Rev 0.00
November 1994 9 J = ABC …
