Datasheet Microchip SY100S331JY — Ficha de datos

NOT RECOMMENDED FOR NEW DESIGNS
Micrel, Inc. TRIPLE D
FLIP-FLOP FEATURES
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в–  SY100S331 SY100S331 DESCRIPTION
The SY100S331 offers three D-type, edge-triggered master/
slave flip-flops with true and complement outputs, designed
for use in high-performance ECL systems. Each flip-flop is
controlled by a common clock (CPc), as well as its own clock
pulse (CPn). The resultant clock signal controlling the flip-flop
is the logical OR operation of these two clock signals. Data
enters the master when both CPc and CPn are LOW and enters
the slave on the rising edge of either CPc or CPn (or both).
Additional control signals include Master Set (MS) and …