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SLIS032B – JULY 1995 – REVISED JUNE 2015 TPIC6B595 Power Logic 8-Bit Shift Register
1 Features 1 Low rDS(on),5 О© (Typical)
Avalanche Energy, 30 mJ
Eight Power DMOS Transistor Outputs of 150-mA
Continuous Current
Output Clamp Voltage, 50 V
Devices are Cascadable
Low-Power Consumption 2 Applications The storage register transfers data to the output
buffer when shift-register clear (SRCLR) is high.
When SRCLR is low, the input shift register is
cleared. When output enable (G) is held high, all data
in the output buffers is held low and all drain outputs
are off. When G is held low, data from the storage
register is transparent to the output buffers. When
data in the output buffers is low, the DMOS-transistor
outputs are off. When data is high, the DMOS
transistor outputs have sink-current capability. The …