Datasheet Texas Instruments TPS51200DRCR — Ficha de datos
| Fabricante | Texas Instruments |
| Serie | TPS51200 |
| Numero de parte | TPS51200DRCR |
Regulador de terminación DDR de sumidero / fuente 3A con referencia tamponada VTTREF para DDR2, DDR3, DDR3L y DDR4 10-VSON -40 a 85
Hojas de datos
TPS51200 Sink and Source DDR Termination Regulator datasheet
PDF, 1.3 Mb, Revisión: C, Archivo publicado: nov 30, 2016
Extracto del documento
Precios
Estado
| Estado del ciclo de vida | Activo (Recomendado para nuevos diseños) |
| Disponibilidad de muestra del fabricante | Sí |
Embalaje
| Pin | 10 |
| Package Type | DRC |
| Industry STD Term | VSON |
| JEDEC Code | S-PDSO-N |
| Package QTY | 3000 |
| Carrier | LARGE T&R |
| Device Marking | 1200 |
| Width (mm) | 3 |
| Length (mm) | 3 |
| Thickness (mm) | .9 |
| Pitch (mm) | .5 |
| Max Height (mm) | 1 |
| Mechanical Data | Descargar |
Paramétricos
| Control Mode | D-CAP,S3,S4/S5 |
| DDR Memory Type | DDR,DDR2,DDR3,DDR3L,DDR4,LPDDR2,LPDDR3 |
| Iout VTT(Max) | 3 A |
| Iq(Typ) | 0.5 mA |
| Operating Temperature Range | -40 to 85 C |
| Output | VREF,VTT |
| Package Group | VSON |
| Package Size: mm2:W x L | 10VSON: 9 mm2: 3 x 3(VSON) PKG |
| Rating | Catalog |
| Regulator Type | Linear Regulator |
| Special Features | S3/S5 Support |
| Vin Bias(Max) | 3.5 V |
| Vin Bias(Min) | 2.375 V |
| Vin(Max) | 3.5 V |
| Vin(Min) | 1.1 V |
| Vout VTT(Min) | 0.6 V |
Plan ecológico
| RoHS | Obediente |
Kits de diseño y Módulos de evaluación
- Evaluation Modules & Boards: TPS51200EVM
TPS51200 Sink Source DDR Termination Regulator
Estado del ciclo de vida: Activo (Recomendado para nuevos diseños) - Evaluation Modules & Boards: EVMX777BG-01-00-00
J6Entry, RSP and TDA2E-17 CPU Board Evaluation Module
Estado del ciclo de vida: Activo (Recomendado para nuevos diseños) - Evaluation Modules & Boards: EVMX777G-01-20-00
J6Entry/RSP Infotainment (CPU+Display+JAMR3) Evaluation Module
Estado del ciclo de vida: Activo (Recomendado para nuevos diseños)
Notas de aplicación
- TMS320C6472 5V Input Pwr Design, Integrated FET DC/DC Converters and ControllersPDF, 452 Kb, Archivo publicado: marzo 26, 2010
This reference design is intended for designers who wish to design up to eight TMS320C6472 Digital Signal Processors into a system using a nominal input voltage of 5 V, with a flexible design using external FETs, and low-dropout regulators for the low-power rails. - Power Ref Design for TMS320C6472 5Vin DC/DC Converters (1x C6472)PDF, 251 Kb, Archivo publicado: marzo 31, 2010
This reference design is intended for designers who wish to design a TMS320C6472 Digital Signal Processor into a system using a nominal input voltage of 5 V, DC/DC converters with integrated FETs, and allowing for ease-of-design and a smaller solution size. - 'C6472 12Vin Flexible Pwr Design Using DCDC Controllers and LDOs (8x C6472)PDF, 441 Kb, Archivo publicado: marzo 26, 2010
This reference design is intended for designers who wish to design up to eight TMS320C6472 Digital Signal Processors into a system using a nominal input voltage of 12 V, external FETs for design flexibility, and low-dropout regulators for the low-power rails. - Power Ref Design for TMS320C6472, 12-Vin Digital Pwr Cntrlrs, and LDOs (Rev. A)PDF, 559 Kb, Revisión: A, Archivo publicado: mayo 24, 2010
This design was created to help those wanting to design a TMS320C6472 digital signal processor into a system using a nominal input of 12 V, having a highly flexible power design, and the ability to monitor temperature as well as dynamically monitoring and controlling voltage and current. - Pwr Ref Design f/'C6472 12-Vin Digital Pwr Controllers and LDOsPDF, 558 Kb, Archivo publicado: abr 28, 2010
This design was created to help designers wishing to design up to eight TMS320C6472 Digital Signal Processors into a system using a nominal input voltage of 12 V, having a highly flexible power design, the ability to monitor temperature, and dynamically monitor and control voltage and current. - Power Reference Design for the 'C6472 12V DCDC Controllers and LDOsPDF, 245 Kb, Archivo publicado: marzo 26, 2010
This reference design is intended for designers who wish to design a TMS320C6472 Digital Signal Processor into a system using a nominal input voltage of 12 V external FETs for design flexibility and low-dropout regulators for the low-power rails. - Intel VR11.1 Server Reference DesignPDF, 38 Kb, Archivo publicado: jul 21, 2010
- Power Two Xilinx(TM) LX240 Virtex-6(TM) DevicesPDF, 63 Kb, Archivo publicado: abr 20, 2010
This reference design is intended to help designers wishing to use two of the new Virtex-6™ LX240 FPGA along with DDR memory and other optional circuitry in their designs. It provides nine rails of lower voltage with an input of 12 volts. The use of PTH T2 modules provides a high-performance solution for good transient response and tight regulation while conserving valuable board space. - LDO PSRR Measurement Simplified (Rev. A)PDF, 131 Kb, Revisión: A, Archivo publicado: agosto 9, 2017
This applicationreportexplainsdifferentmethodsof measuringthe PowerSupplyRejectionRatio(PSRR)of a Low-Dropout(LDO)regulatorand includesthe prosand consof thesemeasuringmethods - LDO Noise Demystified (Rev. A)PDF, 785 Kb, Revisión: A, Archivo publicado: agosto 9, 2017
Thisapplicationreportexplainsthe differencebetweennoiseand PSRRof an LDO.It also explainsthedifferentwaysnoiseis specifiedin LDOdatasheetsandwhichspecificationshouldbe usedin theapplication.Finallyit explainshow LDOnoiseis reduced.
Linea modelo
Serie: TPS51200 (4)
- TPS51200DRCR TPS51200DRCRG4 TPS51200DRCT TPS51200DRCTG4
Clasificación del fabricante
- Semiconductors > Power Management > DDR Memory Power Solutions