Datasheet Texas Instruments OPA4820ID — Ficha de datos

FabricanteTexas Instruments
SerieOPA4820
Numero de parteOPA4820ID
Datasheet Texas Instruments OPA4820ID

Amplificador operacional cuádruple, ganancia unitaria, bajo nivel de ruido y retroalimentación de voltaje 14-SOIC -40 a 85

Hojas de datos

Quad, Unity-Gain, Low-Noise, Voltage-Feedback Operational Amplifier datasheet
PDF, 840 Kb, Revisión: D, Archivo publicado: agosto 28, 2008
Extracto del documento

Precios

Estado

Estado del ciclo de vidaActivo (Recomendado para nuevos diseños)
Disponibilidad de muestra del fabricante

Embalaje

Pin14
Package TypeD
Industry STD TermSOIC
JEDEC CodeR-PDSO-G
Package QTY50
CarrierTUBE
Device MarkingOPA4820
Width (mm)3.91
Length (mm)8.65
Thickness (mm)1.58
Pitch (mm)1.27
Max Height (mm)1.75
Mechanical DataDescargar

Paramétricos

2nd Harmonic84 dBc
3rd Harmonic92 dBc
@ MHz1
Acl, min spec gain1 V/V
Additional FeaturesN/A
ArchitectureBipolar,Voltage FB
BW @ Acl650 MHz
CMRR(Min)76 dB
CMRR(Typ)85 dB
GBW(Typ)650 MHz
Input Bias Current(Max)20000000 pA
Iq per channel(Max)5.85 mA
Iq per channel(Typ)5.6 mA
Number of Channels4
Offset Drift(Typ)4 uV/C
Operating Temperature Range-40 to 85 C
Output Current(Typ)85 mA
Package GroupSOIC
Package Size: mm2:W x L14SOIC: 52 mm2: 6 x 8.65(SOIC) PKG
Rail-to-RailNo
RatingCatalog
Slew Rate(Typ)240 V/us
Total Supply Voltage(Max)12 +5V=5, +/-5V=10
Total Supply Voltage(Min)5 +5V=5, +/-5V=10
Vn at 1kHz(Typ)2.5 nV/rtHz
Vn at Flatband(Typ)2.5 nV/rtHz
Vos (Offset Voltage @ 25C)(Max)0.8 mV

Plan ecológico

RoHSObediente

Kits de diseño y Módulos de evaluación

  • Evaluation Modules & Boards: DEM-OPA-SO-4A
    DEM-OPA-SO-4A
    Estado del ciclo de vida: Activo (Recomendado para nuevos diseños)
  • Evaluation Modules & Boards: DEM-OPA-TSSOP-4A
    DEM-OPA-TSSOP-4A
    Estado del ciclo de vida: Activo (Recomendado para nuevos diseños)

Notas de aplicación

  • RLC Filter Design for ADC Interface Applications (Rev. A)
    PDF, 299 Kb, Revisión: A, Archivo publicado: mayo 13, 2015
    As high performance Analog-to-Digital Converters (ADCs) continue to improve in their performance, the last stage interface from the final amplifier into the converter inputs becomes a critical element in the system design if the full converter dynamic range is desired. This application note describes the performance and design equations for a simple passive 2nd-order filter used successfully in AD
  • ADS5500, OPA695: PC Board Layout for Low Distortion High-Speed ADC Drivers
    PDF, 273 Kb, Archivo publicado: abr 22, 2004
    Once an analog-to-digital converter (ADC) and a driver/interface have been selected for a given application, the next step to achieving excellent performance is laying out the printed circuit board (PCB) that will support the application. This application report describes several techniques for optimizing a high-speed, 14-bit performance, differential driver PCB layout using a wideband operation
  • Measuring Board Parasitics in High-Speed Analog Design
    PDF, 134 Kb, Archivo publicado: jul 7, 2003
    Successful circuit designs using high-speed amplifiers can depend upon understanding and identifying parasitic PCB components. Simulating a design while including PCB parasitics can protect against unpleasant production surprises. This application report discusses an easy method for measuring parasitic components in a prototype or final PC board design by using a standard oscilloscope and low freq

Linea modelo

Clasificación del fabricante

  • Semiconductors > Amplifiers > Operational Amplifiers (Op Amps) > High-Speed Op Amps (>=50MHz)