Datasheet AD744 (Analog Devices) - 12

AD744 Table IV. Performance Summary for the 3 Op Amp
Equation 1 would completely describe the output of the system
Instrumentation Amplifier Circuit
if not for the op amp’s finite slew rate and other nonlinear effects. Even considering these effects, the fine scale settling to
Gain RG Bandwidth T Settle (0.01%)
<0.1% will be determined by the op amp’s small signal behav- 1 NC 3.5 MHz 1.5 µs ior. Equation 1. 2 20 kΩ 2.5 MHz 1.0 µs V 10 2.22 kΩ 1 MHz 2 µs O = – R I ( + ) 100 202 Ω 290 kHz 5 µs IN R C C L X   s2 + GN + RC 2πF  2πF L  s +1 O O Where FO = the op amp’s unity gain crossover frequency   G = the “noise” gain of the circuit 1+ R N  R  O This Equation May Then Be Solved for CL: Equation 2. 2 RC 2πF + 1 ( −G ) X O N C = 2 − GN + L R 2πF R 2πF O O In these equations, capacitance CX is the total capacitance appear- ing at the inverting terminal of the op amp. When modeling an I-to-V converter application, the Norton equivalent circuit of Figure 37. The Pulse Response of the 3 Op Amp Figure 39 can be used directly. Capacitance C Instrumentation Amplifier. Gain = 1, l Horizontal Scale: X is the total capaci- tance of the output of the current source plus the input capacitance 0.5 µV/div., Vertical Scale: 5 V/div. (Gain= 10) of the op amp, which includes any stray capacitance at the op amp’s input.
CCOMP (OPTIONAL) AD744 VOUT RL CLOAD R I R O O CX CL
Figure 39. A Simplified Model of the AD744 Used as a Current-to-Voltage Converter Figure 38. Settling Time of the 3 Op Amp Instrumentation Amplifier. Horizontal Scale: 500 ns/div., Vertical Scale, When RO and IO are replaced with their Thevenin VIN and RIN Pulse Input: 5 V/div., Output Settling: 1 mV/div. equivalents, the general purpose inverting amplifier model of Figure 40 is created. Here capacitor CX represents the input capacitance of the AD744 (5.5 pF) plus any stray capacitance
Minimizing Settling Time in Real-World Applications
due to wiring and the type of IC package employed. An amplifier with a “single pole” or “ideal” integrator open-loop frequency response will achieve the minimum possible settling
CCOMP (OPTIONAL)
time for any given unity-gain bandwidth. However, when this “ideal” amplifier is used in a practical circuit, the actual settling time is increased above the minimum value because of added
AD744 VOUT
time constants which are introduced due to additional capacitance
RL CLOAD
on the amplifier’s summing junction. The following discussion
RIN R
will explain how to minimize this increase in settling time by the selection of the proper value for feedback capacitor, C
V C IN
L.
X CL
If an op amp is modeled as an ideal integrator with a unity gain crossover frequency, fO, Equation 1 will accurately describe the Figure 40. A Simplified Model of the AD744 Used small signal behavior of the circuit of Figure 39. This circuit as an Inverting Amplifier models an op amp connected as an I-to-V converter. REV. C –11–