Datasheet AD654 (Analog Devices) - 11

AD654 +15V 10
m
F +5V +15V MINIMUM A3 = 74LS86 0.1
m
F DISTANCE D 0.1
m
F V4 A3-d R7 68k
V
68k
V
10
m
F 8.2
V
V1 Q1 + V3 1 8 J270 A3-c 2 7 V2 AD654 CT A2 LM360 3 6 100pF 10
m
F 1k
V
Q2 + 4 5 J270 18
V
A3-a VIN 5.9k
V
A3-b 0.1
m
F RT = 1k
V
MINIMUM (0V TO 1V) 1% 470pF DISTANCE – (
3
2) 0.1
m
F A 10
m
F D –5V
Figure 13. 2 MHz, Frequency Doubling V/F
OPERATION AT HIGHER OUTPUT FREQUENCIES
The output of the comparator is a complementary square wave Operation of the AD654 via the conventional output (Pins 1 and at 1 MHz FS. Unlike pulse train output V/F converters, each 2) is speed limited to approximately 500 kHz for reasons of TTL half-cycle of the AD654 output conveys information about the logic compatibility. Although the output stage may become input. Thus it is possible to count edges, rather than full cycles speed limited, the multivibrator core itself is able to oscillate to of the output, and double the effective output frequency. The 1 MHz or more. The designer may take advantage of this feature in XOR gate following A2 acts as an edge detector producing a short order to operate the device at frequencies in excess of 500 kHz. pulse for each input state transition. This effectively doubles the Figure 13 illustrates this with a circuit offering 2 MHz full scale. V/F FS frequency to 2 MHz. The final result is a 1 V full-scale In this circuit the AD654 is operated at a full scale (FS) of 1 mA, input V/F with a 2 MHz full-scale output capability; typical with a C nonlinearity is 0.5%. T of 100 pF. This achieves a basic device FS frequency of 1 MHz across CT. The P channel JFETs, Q1 and Q2, buffer the differential timing capacitor waveforms to a low impedance
2V 5V 500ns
level where the push-pull signal is then ac coupled to the high speed
2V 100 V1
comparator A2. Hysteresis is used, via R7, for nonambiguous
90 0
switching and to eliminate the oscillations which would other-
2V
wise occur at low frequencies.
V2 0
The net result of this is a very high speed circuit which does not
5V
compromise the AD654 dynamic range. This is a result of the FET
V3 10 0
buffers typically having only a few pA of bias current. The high
0% 5V
end dynamic range is limited, however, by parasitic package and
2V 5V V4
layout capacitances in shunt with C
0
T, as well as those from each node to ac ground. Minimizing the lead length between A2–6/A2–7 and Figure 14. Waveforms of 2 MHz Frequency Doubler Q1/Q2 in PC layout will help. A ground plane will also help stability. Figure 14 shows the waveforms V1–V4 found at the respective points shown in Figure 13. –10– REV. C