Datasheet LT1715 (Analog Devices) - 15
| Fabricante | Analog Devices |
| Descripción | 4ns, 150MHz Dual Comparator with Independent Input/Output Supplies |
| Páginas / Página | 20 / 15 — APPLICATIONS INFORMATION. Circuit Description. Figure 9. LT1715 Block … |
| Formato / tamaño de archivo | PDF / 255 Kb |
| Idioma del documento | Inglés |
APPLICATIONS INFORMATION. Circuit Description. Figure 9. LT1715 Block Diagram
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LT1715
APPLICATIONS INFORMATION
ECL, and particularly PECL, is valuable technology for high The input stage topology maximizes the input dynamic speed system design, but it must be used with care. With range available without requiring the power, complexity less than a volt of swing, the noise margins need to be and die area of two complete input stages such as are evaluated carefully. Note that there is some degradation of found in rail-to-rail input comparators. With a single noise margin due to the ±5% resistor selections shown. 2.7V supply, the LT1715 still has a respectable 1.6V of With 10KH/E, there is no temperature compensation of input common mode range. The differential input volt- the logic levels, whereas the LT1715 and the circuits age rangeis rail-to-rail, without the large input currents shown give levels that are stable with temperature. This found incompeting devices. The input stage also features will lower the noise margin over temperature. In some phase reversal protection to prevent false outputs when confi gurations it is possible to add compensation with the inputs are driven below the –100mV common mode diode or transistor junctions in series with the resistors voltage limit. of these networks. The internal hysteresis is implemented by positive, nonlin- For more information on ECL design, refer to the ECLiPS ear feedback around a second gain stage. Until this point, data book (DL140), the 10KH system design handbook the signal path has been entirely differential. The signal (HB205) and PECL design (AN1406), all from Motorola, path is then split into two drive signals for the upper and now ON Semiconductor. lower output transistors. The output transistors are con- nected common emitter for rail-to-rail output operation.
Circuit Description
The Schottky clamps limit the output voltages at about The block diagram of the LT1715 is shown in Figure 9. 300mV from the rail, not quite the 50mV or 15mV of Linear The circuit topology consists of a differential input stage, Technology’s rail-to-rail amplifiers and other products. But again stage with hysteresis and a complementary com- the output of a comparator is digital, and this output stage mon-emitter output stage. All of the internal signal paths can drive TTL or CMOS directly. It can also drive ECL, as utilize low voltage swings for high speed at low power. described earlier, or analog loads. NONLINEAR STAGE +VS + V – CC + +IN + Σ + AV1 A + V2 OUT –IN – Σ – + VEE – GND 1715 F09
Figure 9. LT1715 Block Diagram
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APPLICATIONS INFORMATION
ECL, and particularly PECL, is valuable technology for high The input stage topology maximizes the input dynamic speed system design, but it must be used with care. With range available without requiring the power, complexity less than a volt of swing, the noise margins need to be and die area of two complete input stages such as are evaluated carefully. Note that there is some degradation of found in rail-to-rail input comparators. With a single noise margin due to the ±5% resistor selections shown. 2.7V supply, the LT1715 still has a respectable 1.6V of With 10KH/E, there is no temperature compensation of input common mode range. The differential input volt- the logic levels, whereas the LT1715 and the circuits age rangeis rail-to-rail, without the large input currents shown give levels that are stable with temperature. This found incompeting devices. The input stage also features will lower the noise margin over temperature. In some phase reversal protection to prevent false outputs when confi gurations it is possible to add compensation with the inputs are driven below the –100mV common mode diode or transistor junctions in series with the resistors voltage limit. of these networks. The internal hysteresis is implemented by positive, nonlin- For more information on ECL design, refer to the ECLiPS ear feedback around a second gain stage. Until this point, data book (DL140), the 10KH system design handbook the signal path has been entirely differential. The signal (HB205) and PECL design (AN1406), all from Motorola, path is then split into two drive signals for the upper and now ON Semiconductor. lower output transistors. The output transistors are con- nected common emitter for rail-to-rail output operation.
Circuit Description
The Schottky clamps limit the output voltages at about The block diagram of the LT1715 is shown in Figure 9. 300mV from the rail, not quite the 50mV or 15mV of Linear The circuit topology consists of a differential input stage, Technology’s rail-to-rail amplifiers and other products. But again stage with hysteresis and a complementary com- the output of a comparator is digital, and this output stage mon-emitter output stage. All of the internal signal paths can drive TTL or CMOS directly. It can also drive ECL, as utilize low voltage swings for high speed at low power. described earlier, or analog loads. NONLINEAR STAGE +VS + V – CC + +IN + Σ + AV1 A + V2 OUT –IN – Σ – + VEE – GND 1715 F09
Figure 9. LT1715 Block Diagram
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