Datasheet AD8244 (Analog Devices) - 9
| Fabricante | Analog Devices |
| Descripción | Single-Supply, Low Power, Precision FET Input Quad Buffer |
| Páginas / Página | 21 / 9 — AD8244. Data Sheet. TYPICAL PERFORMANCE CHARACTERISTICS. ITS. –400. –200. … |
| Revisión | A |
| Formato / tamaño de archivo | PDF / 592 Kb |
| Idioma del documento | Inglés |
AD8244. Data Sheet. TYPICAL PERFORMANCE CHARACTERISTICS. ITS. –400. –200. 200. 400. 600. –800. –600. 800. OFFSET VOLTAGE (µV)
Versión de texto del documento
AD8244 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS
VS = ±5 V, TA = 25°C, VIN = 0 V, RL = 10 kΩ, unless otherwise noted.
50 40 40 30 30 ITS ITS H H 20 20 10 10 0 0 –400 –200 0 200 400 600
004
–800 –600 –400 –200 0 200 400 600 800
007
OFFSET VOLTAGE (µV)
1689- 1689- 1
OFFSET VOLTAGE MATCHING (µV)
1 Figure 4. Typical Distribution of Offset Voltage Figure 7. Typical Distribution of Offset Voltage Matching
12 VS = ±15V VIN = ±3V TA = –40°C TO +85°C 40 10 35 8 30 25 ITS 6 H ITS H 20 4 15 10 2 5 0
005
0 –10 –9 –8 –7 –6 –5 –4 –3 –2 –1 0 1 2 3 4 5 6 7 8 9 10 –300 –200 –100 0 100 200 300
008 1689-
OFFSET VOLTAGE DRIFT (µV/°C)
1
SYSTEM ERROR (µV/V)
1689- 1 Figure 5. Typical Distribution of Offset Voltage Drift Figure 8. Typical Distribution of System Error
25 50 VS = ±3V TO ±18V 20 40 15 30 ITS H ITS H 10 20 5 10 0 –0.60 –0.55 –0.50 –0.45 –0.40 –0.35 0
006
–40 –20 0 20 40 60 80
009
INPUT BIAS CURRENT (pA)
1689- 1
PSRR (µV/V)
1689- 1
Figure 6. Typical Distribution of Input Bias Current Figure 9. Typical Distribution of Power Supply Rejection Ratio (PSRR) Rev. A | Page 8 of 20 Document Outline FEATURES APPLICATIONS PIN CONFIGURATION GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION OVERVIEW GUARDING INPUT PROTECTION LAYOUT CONSIDERATIONS DIFFERENTIAL SIGNAL CHAINS LOW OUTPUT IMPEDANCE vs. FREQUENCY APPLICATIONS INFORMATION ELECTROCARDIOGRAM (ECG) FILTERING Sallen-Key Low-Pass Filter Sallen-Key High-Pass Filter Twin-T Notch Filter PHOTODIODE AMPLIFIER LOW NOISE, JFET INPUT BUFFER OUTLINE DIMENSIONS ORDERING GUIDE
VS = ±5 V, TA = 25°C, VIN = 0 V, RL = 10 kΩ, unless otherwise noted.
50 40 40 30 30 ITS ITS H H 20 20 10 10 0 0 –400 –200 0 200 400 600
004
–800 –600 –400 –200 0 200 400 600 800
007
OFFSET VOLTAGE (µV)
1689- 1689- 1
OFFSET VOLTAGE MATCHING (µV)
1 Figure 4. Typical Distribution of Offset Voltage Figure 7. Typical Distribution of Offset Voltage Matching
12 VS = ±15V VIN = ±3V TA = –40°C TO +85°C 40 10 35 8 30 25 ITS 6 H ITS H 20 4 15 10 2 5 0
005
0 –10 –9 –8 –7 –6 –5 –4 –3 –2 –1 0 1 2 3 4 5 6 7 8 9 10 –300 –200 –100 0 100 200 300
008 1689-
OFFSET VOLTAGE DRIFT (µV/°C)
1
SYSTEM ERROR (µV/V)
1689- 1 Figure 5. Typical Distribution of Offset Voltage Drift Figure 8. Typical Distribution of System Error
25 50 VS = ±3V TO ±18V 20 40 15 30 ITS H ITS H 10 20 5 10 0 –0.60 –0.55 –0.50 –0.45 –0.40 –0.35 0
006
–40 –20 0 20 40 60 80
009
INPUT BIAS CURRENT (pA)
1689- 1
PSRR (µV/V)
1689- 1
Figure 6. Typical Distribution of Input Bias Current Figure 9. Typical Distribution of Power Supply Rejection Ratio (PSRR) Rev. A | Page 8 of 20 Document Outline FEATURES APPLICATIONS PIN CONFIGURATION GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION OVERVIEW GUARDING INPUT PROTECTION LAYOUT CONSIDERATIONS DIFFERENTIAL SIGNAL CHAINS LOW OUTPUT IMPEDANCE vs. FREQUENCY APPLICATIONS INFORMATION ELECTROCARDIOGRAM (ECG) FILTERING Sallen-Key Low-Pass Filter Sallen-Key High-Pass Filter Twin-T Notch Filter PHOTODIODE AMPLIFIER LOW NOISE, JFET INPUT BUFFER OUTLINE DIMENSIONS ORDERING GUIDE