Datasheet LTC2201 (Analog Devices) - 6
| Fabricante | Analog Devices |
| Descripción | 16-Bit, 20Msps ADC |
| Páginas / Página | 24 / 6 — The. POWER REQUIREMENTS. denotes the specifi cations which apply over the … |
| Formato / tamaño de archivo | PDF / 1.1 Mb |
| Idioma del documento | Inglés |
The. POWER REQUIREMENTS. denotes the specifi cations which apply over the full operating temperature
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LTC2201
The POWER REQUIREMENTS
l
denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at TA = 25°C. AIN = –1dBFS. (Note 4) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VDD Analog Supply Voltage l 3.135 3.3 3.465 V PSHDN Shutdown Power SHDN = VDD, CLK = VDD 2 mW OVDD Output Supply Voltage l 0.5 3.6 V IVDD Analog Supply Current l 64 80 mA PDIS Power Dissipation l 211 264 mW
TIMING CHARACTERISTICS The
l
denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at TA = 25°C. (Note 4) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
fS Sampling Frequency l 1 20 MHz tL CLK Low Time Duty Cycle Stabilizer Off l 20 25 500 ns Duty Cycle Stabilizer On l 5 25 500 ns tH CLK High Time Duty Cycle Stabilizer Off l 20 25 500 ns Duty Cycle Stabilizer On l 5 25 500 ns tAP Sample-and-Hold 0.9 ns Aperture Delay tD CLK to DATA Delay CL = 5pF (Note 7) l 1.3 3.1 4.9 ns tC CLK to CLKOUT Delay CL = 5pF (Note 7) l 1.3 3.1 4.9 ns tSKEW DATA to CLKOUT Skew CL = 5pF (Note 7) l –0.6 0 0.6 ns DATA Access Time CL = 5pF (Note 7) l 5 15 ns Bus Relinquish Time (Note 7) l 5 15 ns Pipeline 7 Cycles Latency
Note 1:
Stresses beyond those listed under Absolute Maximum Ratings
Note 5:
Integral nonlinearity is defi ned as the deviation of a code from a may cause permanent damage to the device. Exposure to any Absolute “best fi t straight line” to the transfer curve. The deviation is measured from Maximum Rating condition for extended periods may affect device the center of the quantization band. reliability and lifetime.
Note 6:
Offset error is the offset voltage measured from – 1/2LSB when the
Note 2:
All voltage values are with respect to GND, with GND and OGND output code fl ickers between 0000 0000 0000 0000 and 1111 1111 1111 shorted (unless otherwise noted). 1111 in 2’s complement output mode.
Note 3:
When these pin voltages are taken below GND or above VDD, they
Note 7:
Guaranteed by design, not subject to test. will be clamped by internal diodes. This product can handle input currents
Note 8:
Recommended operating conditions. of greater than 100mA below GND or above VDD without latchup.
Note 9:
Dynamic current from switched capacitor inputs is large compared
Note 4:
VDD = 3.3V, fSAMPLE = 20MHz, input range = 2.5VP-P with to DC leakage current, and will vary with sample rate. differential drive (PGA = 0), unless otherwise specifi ed.
Note 10:
Leakage current will experience transient at power up. Keep resistance < 1kΩ. 2201f 6
The POWER REQUIREMENTS
l
denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at TA = 25°C. AIN = –1dBFS. (Note 4) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VDD Analog Supply Voltage l 3.135 3.3 3.465 V PSHDN Shutdown Power SHDN = VDD, CLK = VDD 2 mW OVDD Output Supply Voltage l 0.5 3.6 V IVDD Analog Supply Current l 64 80 mA PDIS Power Dissipation l 211 264 mW
TIMING CHARACTERISTICS The
l
denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at TA = 25°C. (Note 4) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
fS Sampling Frequency l 1 20 MHz tL CLK Low Time Duty Cycle Stabilizer Off l 20 25 500 ns Duty Cycle Stabilizer On l 5 25 500 ns tH CLK High Time Duty Cycle Stabilizer Off l 20 25 500 ns Duty Cycle Stabilizer On l 5 25 500 ns tAP Sample-and-Hold 0.9 ns Aperture Delay tD CLK to DATA Delay CL = 5pF (Note 7) l 1.3 3.1 4.9 ns tC CLK to CLKOUT Delay CL = 5pF (Note 7) l 1.3 3.1 4.9 ns tSKEW DATA to CLKOUT Skew CL = 5pF (Note 7) l –0.6 0 0.6 ns DATA Access Time CL = 5pF (Note 7) l 5 15 ns Bus Relinquish Time (Note 7) l 5 15 ns Pipeline 7 Cycles Latency
Note 1:
Stresses beyond those listed under Absolute Maximum Ratings
Note 5:
Integral nonlinearity is defi ned as the deviation of a code from a may cause permanent damage to the device. Exposure to any Absolute “best fi t straight line” to the transfer curve. The deviation is measured from Maximum Rating condition for extended periods may affect device the center of the quantization band. reliability and lifetime.
Note 6:
Offset error is the offset voltage measured from – 1/2LSB when the
Note 2:
All voltage values are with respect to GND, with GND and OGND output code fl ickers between 0000 0000 0000 0000 and 1111 1111 1111 shorted (unless otherwise noted). 1111 in 2’s complement output mode.
Note 3:
When these pin voltages are taken below GND or above VDD, they
Note 7:
Guaranteed by design, not subject to test. will be clamped by internal diodes. This product can handle input currents
Note 8:
Recommended operating conditions. of greater than 100mA below GND or above VDD without latchup.
Note 9:
Dynamic current from switched capacitor inputs is large compared
Note 4:
VDD = 3.3V, fSAMPLE = 20MHz, input range = 2.5VP-P with to DC leakage current, and will vary with sample rate. differential drive (PGA = 0), unless otherwise specifi ed.
Note 10:
Leakage current will experience transient at power up. Keep resistance < 1kΩ. 2201f 6