Datasheet LTC2230, LTC2231 (Analog Devices)
| Fabricante | Analog Devices |
| Descripción | 10-Bit, 135Msps ADCs |
| Páginas / Página | 32 / 1 — FEATURES. DESCRIPTIO. Sample Rate: 170Msps/135 Msps. 61dB SNR up to … |
| Formato / tamaño de archivo | PDF / 718 Kb |
| Idioma del documento | Inglés |
FEATURES. DESCRIPTIO. Sample Rate: 170Msps/135 Msps. 61dB SNR up to 140MHz Input. 75dB SFDR up to 200MHz Input
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LTC2230/LTC2231 10-Bit,170Msps/ 135Msps ADCs
U FEATURES DESCRIPTIO
■
Sample Rate: 170Msps/135 Msps
The LTC®2230 and LTC2231 are 170Msps/135Msps, sam- ■
61dB SNR up to 140MHz Input
pling 10-bit A/D converters designed for digitizing high ■
75dB SFDR up to 200MHz Input
frequency, wide dynamic range signals. The LTC2230/ ■
775MHz Full Power Bandwidth S/H
LTC2231 are perfect for demanding communications ■
Single 3.3V Supply
applications with AC performance that includes 61dB SNR ■
Low Power Dissipation: 890mW/660mW
and 75dB spurious free dynamic range for signals ■ LVDS, CMOS, or Demultiplexed CMOS Outputs up to 200MHz. Ultralow jitter of 0.15psRMS allows ■ Selectable Input Ranges: ±0.5V or ±1V undersampling of IF frequencies with excellent noise ■ No Missing Codes performance. ■ Optional Clock Duty Cycle Stabilizer DC specs include ±0.2LSB INL (typ), ±0.1LSB DNL (typ) ■ Shutdown and Nap Modes and no missing codes over temperature. The transition ■ Data Ready Output Clock noise is a low 0.12LSB ■ Pin Compatible Family RMS. 185Msps: LTC2220-1 (12-Bit) The digital outputs can be either differential LVDS, or 170Msps: LTC2220 (12-Bit), LTC2230 (10-Bit) single-ended CMOS. There are three format options for 135Msps: LTC2221 (12-Bit), LTC2231 (10-Bit) the CMOS outputs: a single bus running at the full data rate ■ 64-Pin 9mm x 9mm QFN Package or two demultiplexed buses running at half data rate with
U
either interleaved or simultaneous update. A separate
APPLICATIO S
output power supply allows the CMOS output swing to range from 0.5V to 3.6V. ■ Wireless and Wired Broadband Communication The ENC+ and ENC– inputs may be driven differentially or ■ Cable Head-End Systems single ended with a sine wave, PECL, LVDS, TTL, or CMOS ■ Power Amplifier Linearization inputs. An optional clock duty cycle stabilizer allows high ■ Communications Test Equipment performance at full speed for a wide range of clock duty , LT, LTC and LTM are registered trademarks of Linear Technology Corporation. cycles. All other trademarks are the property of their respective owners.
U TYPICAL APPLICATIO
3.3V V
SFDR vs Input Frequency
DD 90 REFH FLEXIBLE 0.5V 85 REFL REFERENCE TO 3.6V 4th OR HIGHER 80 OVDD 75 + D9 70 10-BIT • CMOS ANALOG INPUT CORRECTION OUTPUT 2nd OR 3rd PIPELINED • OR INPUT 65 S/H LOGIC DRIVERS ADC CORE • LVDS – D0 SFDR (dBFS) 60 55 OGND 50 CLOCK/DUTY 45 CYCLE 40 CONTROL 0 100 200 300 400 500 600 INPUT FREQUENCY (MHz) 22301 TA01 2230 TA01b ENCODE INPUT 22301fb 1
U FEATURES DESCRIPTIO
■
Sample Rate: 170Msps/135 Msps
The LTC®2230 and LTC2231 are 170Msps/135Msps, sam- ■
61dB SNR up to 140MHz Input
pling 10-bit A/D converters designed for digitizing high ■
75dB SFDR up to 200MHz Input
frequency, wide dynamic range signals. The LTC2230/ ■
775MHz Full Power Bandwidth S/H
LTC2231 are perfect for demanding communications ■
Single 3.3V Supply
applications with AC performance that includes 61dB SNR ■
Low Power Dissipation: 890mW/660mW
and 75dB spurious free dynamic range for signals ■ LVDS, CMOS, or Demultiplexed CMOS Outputs up to 200MHz. Ultralow jitter of 0.15psRMS allows ■ Selectable Input Ranges: ±0.5V or ±1V undersampling of IF frequencies with excellent noise ■ No Missing Codes performance. ■ Optional Clock Duty Cycle Stabilizer DC specs include ±0.2LSB INL (typ), ±0.1LSB DNL (typ) ■ Shutdown and Nap Modes and no missing codes over temperature. The transition ■ Data Ready Output Clock noise is a low 0.12LSB ■ Pin Compatible Family RMS. 185Msps: LTC2220-1 (12-Bit) The digital outputs can be either differential LVDS, or 170Msps: LTC2220 (12-Bit), LTC2230 (10-Bit) single-ended CMOS. There are three format options for 135Msps: LTC2221 (12-Bit), LTC2231 (10-Bit) the CMOS outputs: a single bus running at the full data rate ■ 64-Pin 9mm x 9mm QFN Package or two demultiplexed buses running at half data rate with
U
either interleaved or simultaneous update. A separate
APPLICATIO S
output power supply allows the CMOS output swing to range from 0.5V to 3.6V. ■ Wireless and Wired Broadband Communication The ENC+ and ENC– inputs may be driven differentially or ■ Cable Head-End Systems single ended with a sine wave, PECL, LVDS, TTL, or CMOS ■ Power Amplifier Linearization inputs. An optional clock duty cycle stabilizer allows high ■ Communications Test Equipment performance at full speed for a wide range of clock duty , LT, LTC and LTM are registered trademarks of Linear Technology Corporation. cycles. All other trademarks are the property of their respective owners.
U TYPICAL APPLICATIO
3.3V V
SFDR vs Input Frequency
DD 90 REFH FLEXIBLE 0.5V 85 REFL REFERENCE TO 3.6V 4th OR HIGHER 80 OVDD 75 + D9 70 10-BIT • CMOS ANALOG INPUT CORRECTION OUTPUT 2nd OR 3rd PIPELINED • OR INPUT 65 S/H LOGIC DRIVERS ADC CORE • LVDS – D0 SFDR (dBFS) 60 55 OGND 50 CLOCK/DUTY 45 CYCLE 40 CONTROL 0 100 200 300 400 500 600 INPUT FREQUENCY (MHz) 22301 TA01 2230 TA01b ENCODE INPUT 22301fb 1