Datasheet LTC2424, LTC2428 (Analog Devices) - 14
| Fabricante | Analog Devices |
| Descripción | 4-/8-Channel 20-Bit µPower No Latency ∆ΣTM ADCs |
| Páginas / Página | 36 / 14 — APPLICATIONS INFORMATION. Figure 4. Typical Data Input/Output Timing. … |
| Formato / tamaño de archivo | PDF / 431 Kb |
| Idioma del documento | Inglés |
APPLICATIONS INFORMATION. Figure 4. Typical Data Input/Output Timing. Table 2. LTC2424/LTC2428 Output Data Format. Bit 23
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LTC2424/LTC2428
U U W U APPLICATIONS INFORMATION
tCONV CSMUX/CSADC SDO Hi-Z EOC “0” SIG EXT MSB LSB Hi-Z BIT 23 BIT 22 BIT 0 SCK/CLK DIN EN D2 D1 D0 DON’T CARE 24248 F04
Figure 4. Typical Data Input/Output Timing Table 2. LTC2424/LTC2428 Output Data Format Bit 23 Bit 22 Bit 21 Bit 20 Bit 19 Bit 18 Bit 17 Bit 16 Bit 15 … Bit 0 Input Voltage EOC DMY SIG EXR MSB LSB
VIN > 9/8 • VREF 0 0 1 1 0 0 0 1 1 ... 1 9/8 • VREF 0 0 1 1 0 0 0 1 1 ... 1 VREF + 1LSB 0 0 1 1 0 0 0 0 0 ... 0 VREF 0 0 1 0 1 1 1 1 1 ... 1 3/4VREF + 1LSB 0 0 1 0 1 1 0 0 0 ... 0 3/4VREF 0 0 1 0 1 0 1 1 1 ... 1 1/2VREF + 1LSB 0 0 1 0 1 0 0 0 0 ... 0 1/2VREF 0 0 1 0 0 1 1 1 1 ... 1 1/4VREF + 1LSB 0 0 1 0 0 1 0 0 0 ... 0 1/4VREF 0 0 1 0 0 0 1 1 1 ... 1 0+/0– 0 0 1/0* 0 0 0 0 0 0 ... 0 –1LSB 0 0 0 1 1 1 1 1 1 ... 1 –1/8 • VREF 0 0 0 1 1 1 1 0 0 ... 0 VIN < –1/8 • VREF 0 0 0 1 1 1 1 0 0 ... 0 *The sign bit changes state during the 0 code. As long as the voltage on the VIN pin is maintained within
Channel Selection
the – 0.3V to (VCC + 0.3V) absolute maximum operating Typically, CSADC and CSMUX are tied together or CSADC range, a conversion result is generated for any input value is inverted and drives CSMUX. SCK and CLK are tied from – 0.125 • VREF to 1.125 • VREF. For input voltages together and driven with a common clock signal. During greater than 1.125 • VREF, the conversion result is clamped channel selection, CSMUX is HIGH. Data is shifted into the to the value corresponding to 1.125 • VREF. For input D voltages below – 0.125 • V IN pin on the rising edge of CLK, see Figure 4. Table 3 REF, the conversion result is shows the bit combinations for channel selection. In order clamped to the value corresponding to – 0.125 • VREF. to enable the multiplexer output, CSMUX must be pulled 14
U U W U APPLICATIONS INFORMATION
tCONV CSMUX/CSADC SDO Hi-Z EOC “0” SIG EXT MSB LSB Hi-Z BIT 23 BIT 22 BIT 0 SCK/CLK DIN EN D2 D1 D0 DON’T CARE 24248 F04
Figure 4. Typical Data Input/Output Timing Table 2. LTC2424/LTC2428 Output Data Format Bit 23 Bit 22 Bit 21 Bit 20 Bit 19 Bit 18 Bit 17 Bit 16 Bit 15 … Bit 0 Input Voltage EOC DMY SIG EXR MSB LSB
VIN > 9/8 • VREF 0 0 1 1 0 0 0 1 1 ... 1 9/8 • VREF 0 0 1 1 0 0 0 1 1 ... 1 VREF + 1LSB 0 0 1 1 0 0 0 0 0 ... 0 VREF 0 0 1 0 1 1 1 1 1 ... 1 3/4VREF + 1LSB 0 0 1 0 1 1 0 0 0 ... 0 3/4VREF 0 0 1 0 1 0 1 1 1 ... 1 1/2VREF + 1LSB 0 0 1 0 1 0 0 0 0 ... 0 1/2VREF 0 0 1 0 0 1 1 1 1 ... 1 1/4VREF + 1LSB 0 0 1 0 0 1 0 0 0 ... 0 1/4VREF 0 0 1 0 0 0 1 1 1 ... 1 0+/0– 0 0 1/0* 0 0 0 0 0 0 ... 0 –1LSB 0 0 0 1 1 1 1 1 1 ... 1 –1/8 • VREF 0 0 0 1 1 1 1 0 0 ... 0 VIN < –1/8 • VREF 0 0 0 1 1 1 1 0 0 ... 0 *The sign bit changes state during the 0 code. As long as the voltage on the VIN pin is maintained within
Channel Selection
the – 0.3V to (VCC + 0.3V) absolute maximum operating Typically, CSADC and CSMUX are tied together or CSADC range, a conversion result is generated for any input value is inverted and drives CSMUX. SCK and CLK are tied from – 0.125 • VREF to 1.125 • VREF. For input voltages together and driven with a common clock signal. During greater than 1.125 • VREF, the conversion result is clamped channel selection, CSMUX is HIGH. Data is shifted into the to the value corresponding to 1.125 • VREF. For input D voltages below – 0.125 • V IN pin on the rising edge of CLK, see Figure 4. Table 3 REF, the conversion result is shows the bit combinations for channel selection. In order clamped to the value corresponding to – 0.125 • VREF. to enable the multiplexer output, CSMUX must be pulled 14