Datasheet LT3580 (Analog Devices) - 15

LT3580
APPLICATIONS INFORMATION
so they should not be used for calculating efficiency in
VIN Ramp Rate
discontinuous mode or at light load currents. While initially powering a switching converter application, •I the V Average Input Current : I = VOUT OUT IN ramp rate should be limited. High VIN ramp rates can IN V • η cause excessive inrush currents in the passive components IN of the converter. This can lead to current and/or voltage Switch I2R Loss: P = (DC)(I )2(R ) overstress and may damage the passive components or SW IN SW the chip. Ramp rates less than 500mV/μs, depending on Base Drive Loss (AC): P =13n(I )(V )(f) BAC IN OUT component parameters, will generally prevent these issues. )(I )(DC) Also, be careful to avoid hot-plugging. Hot-plugging occurs Base Drive Loss (DC): P = (VIN IN BDC when an active voltage supply is “instantly” connected or 50 switched to the input of the converter. Hot-plugging results Input Power Loss: P =7mA(V ) in very fast input ramp rates and is not recommended. INP IN Finally, for more information, refer to Linear application where: note AN88, which discusses voltage overstress that can RSW = switch resistance (typically 200mΩ at 1.5A) occur when an inductive source impedance is hot-plugged DC = duty cycle (see the Power Switch Duty Cycle sec- to an input pin bypassed by ceramic capacitors. tion for formulas)
Layout Hints
η = power conversion efficiency (typically 88% at high As with all high frequency switchers, when considering currents) layout, care must be taken to achieve optimal electrical, Example: boost configuration, VIN = 5V, VOUT = 12V, thermal and noise performance. One will not get adver- IOUT = 0.5A, f = 1.25MHz, VD = 0.5V: tised performance with a careless layout. For maximum I efficiency, switch rise and fall times are typically in the IN = 1.36A 5ns to 10ns range. To prevent noise, both radiated and DC = 61.5% conducted, the high speed switching current path, shown in P Figure 8, must be kept as short as possible. This is imple- SW = 228mW mented in the suggested layout of a boost configuration in PBAC = 270mW Figure 9. Shortening this path will also reduce the parasitic PBDC = 84mW trace inductance. At switch-off, this parasitic inductance produces a flyback spike across the LT3580 switch. When PINP = 35mW operating at higher currents and output voltages, with poor Total LT3580 power dissipation (PTOT) = 617mW layout, this spike can generate voltages across the LT3580 Thermal resistance for the LT3580 is influenced by the pres- that may exceed its absolute maximum rating. A ground ence of internal, topside or backside planes. To calculate plane should also be used under the switcher circuitry to die temperature, use the appropriate thermal resistance prevent interplane coupling and overall noise. number and add in worst-case ambient temperature: The VC and FB components should be kept as far away T as practical from the switch node. The ground for these J = TA + θJA • PTOT components should be separated from the switch cur- where TJ = junction temperature, TA = ambient tempera- rent path. Failure to do so can result in poor stability or ture, θJA = 43°C/W for the 3mm × 3mm DFN package and subharmonic oscillation. 35°C/W to 40°C/W for the MSOP Exposed Pad package. PTOT is calculated above. 3580fg 15