Datasheet LTC3422 (Analog Devices) - 8

LTC3422
U OPERATIO
inrush current limiting are provided during start-up as oscillator, the free running frequency must be set at least well as normal switching mode. The same soft-start 20% lower than the desired synchronized frequency. capacitor is used for each operating mode. When either V f = 28 IN or VOUT exceeds 2.25V, the LTC3422 OSC RT enters normal operating mode. Once the output voltage exceeds the input by 0.3V typical, the LTC3422 powers where fOSC is in MHz and RT is in kΩ. itself from VOUT instead of VIN. At this point the internal circuitry has no dependency on the V
Current Sensing
IN input voltage, eliminating the requirement for a large input capacitor. Lossless current sensing converts the peak current signal The input voltage can drop as low as 0.5V without affecting to a voltage to sum in with the internal slope compensa- circuit operation. The limiting factor for the application tion. This summed signal is compared to the error ampli- becomes the availability of the power source to supply fier output to provide a peak current control command for sufficient energy to the output at the low voltages and the the PWM. The LTC3422 incorporates slope compensation maximum duty cycle, which is clamped at 91% typical. which is adaptive to the input and output voltages. There- fore, the converter provides the proper amount of slope
LOW NOISE FIXED FREQUENCY OPERATION
compensation to ensure stability, but not an excess which would cause a loss of phase margin in the converter.
Shutdown Error Amplifier
The part is shutdown by pulling SHDN below 0.25V, and activated by pulling the pin initially above 1V. Once VOUT The error amplifier is a transconductance amplifier, with exceeds 2.2V typical, hysteresis is applied to this pin its positive input internally connected to the 1.216V refer- allowing it to maintain a logic high state down to 0.65V. ence and its negative input connected to FB. A simple Note that SHDN can be driven above VIN or VOUT as long compensation network is placed from VC to ground. as it is limited to less than the absolute maximum rating. Internal clamps limit the minimum and maximum error amplifier output voltage for improved large-signal tran-
Soft-Start
sient response. The soft-start time is programmed with an external capaci-
Current Limit
tor from SS to ground. An internal current source charges it with a nominal 2.4µA. The ramping voltage on SS The current limit circuitry shuts off the internal N-channel dictates the gradually increasing peak current limit until MOSFET switch when the current limit threshold is reached. the voltage on the capacitor exceeds 1.6V, after which the In Burst Mode operation, the current limit is reduced to internally set peak current limit is maintained. In the event approximately 600mA. of a commanded shutdown or a thermal shutdown, the capacitor on SS is discharged to ground automatically.
Zero Current Amplifier
Note that Burst Mode operation is inhibited during the The zero current amplifier monitors the inductor current to soft-start time. the output and shuts off the synchronous rectifier once the t (ms) = C current falls below 50mA typical, preventing negative SS (µF) • 320 inductor current.
Oscillator Anti-Ringing Control
The frequency of operation is set through a resistor from R The anti-ringing control connects a resistor across the T to ground. A precision timing capacitor resides inside the LTC3422. The oscillator can be synchronized with an inductor to dampen the ringing on SW during discontinu- external clock applied to SYNC. When synchronizing the ous conduction mode. The LCSW ringing (L = inductor, 3422fa 8