Datasheet AD7616-P (Analog Devices) - 38
| Fabricante | Analog Devices |
| Descripción | 16-Channel DAS with 16-Bit, Bipolar Input, Dual Simultaneous Sampling ADC with Parallel Interface |
| Páginas / Página | 47 / 38 — Data Sheet. AD7616-P. CONFIGURATION REGISTER. Address: 0x02, Reset: … |
| Formato / tamaño de archivo | PDF / 862 Kb |
| Idioma del documento | Inglés |
Data Sheet. AD7616-P. CONFIGURATION REGISTER. Address: 0x02, Reset: 0x0000, Name: Configuration Register
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Data Sheet AD7616-P CONFIGURATION REGISTER
The configuration register is used in software mode to configure many of the main functions of the ADC, including the sequencer, burst mode, oversampling, and CRC options.
Address: 0x02, Reset: 0x0000, Name: Configuration Register
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[15:9] Addressing (R/W) [0] CRCEN (R/W)
CRC Enable
[8] RESERVED [1] STATUSEN (R/W) [7] SDEF (R)
Status Regis ter Output Enable Self-Detector Error flag
[4:2] OS (R/W) [6] BURSTEN (R/W)
OS ratio s am ples per channel Burs t Mode enable 000: OS1. 001: OS2. 010: OS4. 011: OS8. 100: OS16. 101: OS32. 110: OS64. 111: OS128.
[5] SEQEN (R/W)
Channel Sequencer Enable
Table 19. Bit Descriptions for the Configuration Register Bits Bit Name Settings Description Reset1 Access
[15:9] Addressing 0 Bits[15:9] define the address of the relevant register. See the Addressing Registers 0x0 RW section for further details. 8 RESERVED Reserved. 0x0 R/W 7 SDEF Self detector error flag. N/A R 0 Test passed. The AD7616-P configured itself after power-up. 1 Test failed. An issue was detected during device configuration. A reset is required. 6 BURSTEN Burst mode enable. 0x0 RW 0 Burst mode is disabled. Each channel pair to be converted requires a CONVST pulse. 1 A single CONVST pulse converts every channel pair programmed in the 32-layer sequencer stack registers up to and including the layer defined by the SSRENx bit. See the Software Mode Sequencer section and the Software Mode Burst section for further details. 5 SEQEN Channel sequencer enable. 0x0 RW 0 The channel sequencer is disabled. 1 The channel sequencer is enabled. [4:2] OS Oversampling (OS) ratio, samples per channel. 0x0 RW 000 Oversampling disabled. 001 Oversampling enabled, OSR = 2. 010 Oversampling enabled, OSR = 4. 011 Oversampling enabled, OSR = 8. 100 Oversampling enabled, OSR = 16. 101 Oversampling enabled, OSR = 32. 110 Oversampling enabled, OSR = 64. 111 Oversampling enabled, OSR = 128. 1 STATUSEN Status register output enable. 0x0 RW 0 The status register is not read out when reading the conversion result. 1 The status register is read out at the end of all the conversion words (including the self test channel if enabled in sequencer mode) if all the selected channels are read out. The CRC result is included in the last eight bits. 0 CRCEN CRC enable. The STATUSEN and CRCEN bits have identical functionality. 0x0 RW 1 N/A means not applicable. Rev. 0 | Page 37 of 46 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING SPECIFICATIONS Universal Timing Specifications Parallel Interface Timing Specifications ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION CONVERTER DETAILS ANALOG INPUT Analog Input Channel Selection Analog Input Ranges Analog Input Impedance Analog Input Clamp Protection Analog Input Antialiasing Filter ADC TRANSFER FUNCTION INTERNAL/EXTERNAL REFERENCE SHUTDOWN MODE DIGITAL FILTER APPLICATIONS INFORMATION FUNCTIONALITY OVERVIEW POWER SUPPLIES TYPICAL CONNECTIONS DEVICE CONFIGURATION OPERATIONAL MODE INTERNAL/EXTERNAL REFERENCE HARDWARE MODE SOFTWARE MODE RESET FUNCTIONALITY PIN FUNCTION OVERVIEW DIGITAL INTERFACE CHANNEL SELECTION Hardware Mode Software Mode PARALLEL INTERFACE Reading Conversion Results Writing Register Data Reading Register Data SEQUENCER HARDWARE MODE SEQUENCER SOFTWARE MODE SEQUENCER BURST SEQUENCER Hardware Mode Burst Software Mode Burst DIAGNOSTICS DIAGNOSTIC CHANNELS INTERFACE SELF TEST CRC REGISTER SUMMARY ADDRESSING REGISTERS CONFIGURATION REGISTER CHANNEL REGISTER INPUT RANGE REGISTERS Input Range Register A1 Input Range Register A2 Input Range Register B1 Input Range Register B2 SEQUENCER STACK REGISTERS Sequencer Stack Register 0 to Sequencer Stack Register 7 Sequencer Stack Register 8 to Sequencer Stack Register 31 STATUS REGISTER OUTLINE DIMENSIONS ORDERING GUIDE
Data Sheet AD7616-P CONFIGURATION REGISTER
The configuration register is used in software mode to configure many of the main functions of the ADC, including the sequencer, burst mode, oversampling, and CRC options.
Address: 0x02, Reset: 0x0000, Name: Configuration Register
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[15:9] Addressing (R/W) [0] CRCEN (R/W)
CRC Enable
[8] RESERVED [1] STATUSEN (R/W) [7] SDEF (R)
Status Regis ter Output Enable Self-Detector Error flag
[4:2] OS (R/W) [6] BURSTEN (R/W)
OS ratio s am ples per channel Burs t Mode enable 000: OS1. 001: OS2. 010: OS4. 011: OS8. 100: OS16. 101: OS32. 110: OS64. 111: OS128.
[5] SEQEN (R/W)
Channel Sequencer Enable
Table 19. Bit Descriptions for the Configuration Register Bits Bit Name Settings Description Reset1 Access
[15:9] Addressing 0 Bits[15:9] define the address of the relevant register. See the Addressing Registers 0x0 RW section for further details. 8 RESERVED Reserved. 0x0 R/W 7 SDEF Self detector error flag. N/A R 0 Test passed. The AD7616-P configured itself after power-up. 1 Test failed. An issue was detected during device configuration. A reset is required. 6 BURSTEN Burst mode enable. 0x0 RW 0 Burst mode is disabled. Each channel pair to be converted requires a CONVST pulse. 1 A single CONVST pulse converts every channel pair programmed in the 32-layer sequencer stack registers up to and including the layer defined by the SSRENx bit. See the Software Mode Sequencer section and the Software Mode Burst section for further details. 5 SEQEN Channel sequencer enable. 0x0 RW 0 The channel sequencer is disabled. 1 The channel sequencer is enabled. [4:2] OS Oversampling (OS) ratio, samples per channel. 0x0 RW 000 Oversampling disabled. 001 Oversampling enabled, OSR = 2. 010 Oversampling enabled, OSR = 4. 011 Oversampling enabled, OSR = 8. 100 Oversampling enabled, OSR = 16. 101 Oversampling enabled, OSR = 32. 110 Oversampling enabled, OSR = 64. 111 Oversampling enabled, OSR = 128. 1 STATUSEN Status register output enable. 0x0 RW 0 The status register is not read out when reading the conversion result. 1 The status register is read out at the end of all the conversion words (including the self test channel if enabled in sequencer mode) if all the selected channels are read out. The CRC result is included in the last eight bits. 0 CRCEN CRC enable. The STATUSEN and CRCEN bits have identical functionality. 0x0 RW 1 N/A means not applicable. Rev. 0 | Page 37 of 46 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING SPECIFICATIONS Universal Timing Specifications Parallel Interface Timing Specifications ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION CONVERTER DETAILS ANALOG INPUT Analog Input Channel Selection Analog Input Ranges Analog Input Impedance Analog Input Clamp Protection Analog Input Antialiasing Filter ADC TRANSFER FUNCTION INTERNAL/EXTERNAL REFERENCE SHUTDOWN MODE DIGITAL FILTER APPLICATIONS INFORMATION FUNCTIONALITY OVERVIEW POWER SUPPLIES TYPICAL CONNECTIONS DEVICE CONFIGURATION OPERATIONAL MODE INTERNAL/EXTERNAL REFERENCE HARDWARE MODE SOFTWARE MODE RESET FUNCTIONALITY PIN FUNCTION OVERVIEW DIGITAL INTERFACE CHANNEL SELECTION Hardware Mode Software Mode PARALLEL INTERFACE Reading Conversion Results Writing Register Data Reading Register Data SEQUENCER HARDWARE MODE SEQUENCER SOFTWARE MODE SEQUENCER BURST SEQUENCER Hardware Mode Burst Software Mode Burst DIAGNOSTICS DIAGNOSTIC CHANNELS INTERFACE SELF TEST CRC REGISTER SUMMARY ADDRESSING REGISTERS CONFIGURATION REGISTER CHANNEL REGISTER INPUT RANGE REGISTERS Input Range Register A1 Input Range Register A2 Input Range Register B1 Input Range Register B2 SEQUENCER STACK REGISTERS Sequencer Stack Register 0 to Sequencer Stack Register 7 Sequencer Stack Register 8 to Sequencer Stack Register 31 STATUS REGISTER OUTLINE DIMENSIONS ORDERING GUIDE