Datasheet ADAS3023 (Analog Devices) - 28

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Data Sheet ADAS3023
to access the data result prior to initiating a new conversion interface uses the CS, SCK, SDO, and DIN signals. Timing signals produces an invalid result. for a serial interface are shown in Figure 47. Upon the device returning from power-down mode or from a reset SDO is activated when CS is asserted. The conversion result is when the default CFG is not used, there is no tACQ requirement output on SDO and updated on the SCK falling edges. Simulta- because the first two conversions from power-up are undefined/ neously, the 16-bit CFG word is updated, if needed, on the serial invalid because the one-deep delay pipeline requirement must data input (DIN). The state of BUSY/SDO2 (Bit 0) determines the be satisfied to reconfigure the device to the desired setting. output format of the MSB data when SDO is activated after the
SERIAL DATA INTERFACE
EOC. Note that, in Figure 47, SCK is shown as idling high. SCK can idle high or low, requiring the system developer to design an The ADAS3023 uses a simple 4-wire interface and is compatible interface that suits setup and hold times for both SDO and DIN. with FPGAs, DSPs, and common serial interfaces such as a serial peripheral interface (SPI), QSPI™, and MICROWIRE®. The
tSCK t t SCKH DIS tSCKL CS SCK tSDOH tEN tSDOV SDO (MISO) DIN (MOSI) tDINS
018
tDINH
10942- Figure 47. Serial Timing Rev. A | Page 27 of 32 Document Outline Features Applications Functional Block Diagram General Description Table of Contents Revision History Specifications Timing Specifications Circuit and Voltage Diagrams Timing Diagrams Absolute Maximum Ratings ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Terminology Theory of Operation Overview Operation Transfer Functions Typical Application Connection Diagram Analog Inputs Input Structure Programmable Gain Common-Mode Operating Range Single-Ended Signals with a Nonzero DC Offset (Asymmetrical) Single-Ended Signals with a 0 V DC Offset (Symmetrical) Voltage Reference Input/Output Internal Reference External Reference and Internal Buffer External Reference Reference Decoupling Power Supply Core Supplies High Voltage Supplies Power Dissipation Modes Fully Operational Mode Power-Down Mode Conversion Modes Warp Mode (CMS = 0) Normal Mode (CMS = 1, Default) Digital Interface Conversion Control CNV Rising--Start of Conversion (SOC) BUSY/SDO2 Falling Edge—End of Conversion (EOC) Register Pipeline RESET and Power-Down (PD) Inputs Serial Data Interface General Timing Configuration Register Packaging and Ordering Information Outline Dimensions Ordering Guide