Datasheet AD9683 (Analog Devices) - 3
| Fabricante | Analog Devices |
| Descripción | 14-Bit, 170 MSPS/250 MSPS, JESD204B, Analog-to-Digital Converter |
| Páginas / Página | 45 / 3 — AD9683. Data Sheet. TABLE OF CONTENTS. REVISION HISTORY 6/2016—Rev. C to … |
| Revisión | D |
| Formato / tamaño de archivo | PDF / 1.4 Mb |
| Idioma del documento | Inglés |
AD9683. Data Sheet. TABLE OF CONTENTS. REVISION HISTORY 6/2016—Rev. C to Rev.D. 9/2015—Rev. B to Rev. C. 2/2014—Rev. 0 to Rev. A
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AD9683 Data Sheet TABLE OF CONTENTS
Features .. 1 Power Dissipation and Standby Mode .. 23 Applications ... 1 Digital Outputs ... 24 Functional Block Diagram .. 1 JESD204B Transmit Top Level Description .. 24 General Description ... 1 ADC Overrange and Gain Control .. 29 Revision History ... 2 DC Correction (DCC) ... 31 Product Highlights ... 3 DC Correction Bandwidth .. 31 Specifications ... 4 DC Correction Readback .. 31 ADC DC Specifications ... 4 DC Correction Freeze .. 31 ADC AC Specifications ... 5 DC Correction Enable Bits ... 31 Digital Specifications ... 6 Serial Port Interface (SPI) .. 32 Switching Specifications .. 8 Configuration Using the SPI ... 32 Timing Specifications .. 9 Hardware Interface ... 32 Absolute Maximum Ratings .. 10 SPI Accessible Features .. 33 Thermal Characteristics .. 10 Memory Map .. 34 ESD Caution .. 10 Reading the Memory Map Register Table ... 34 Pin Configuration and Function Descriptions ... 11 Memory Map Register Table ... 35 Typical Performance Characteristics ... 13 Memory Map Register Descriptions .. 39 Equivalent Circuits ... 18 Applications Information .. 43 Theory of Operation .. 19 Design Guidelines .. 43 ADC Architecture .. 19 Outline Dimensions ... 44 Analog Input Considerations .. 19 Ordering Guide .. 44 Voltage Reference ... 20 Clock Input Considerations .. 21
REVISION HISTORY 6/2016—Rev. C to Rev.D
Changes to SYNCINB+ Pin Description .. 11 Changes to Table 17 .. 37 Changes to Transfer Register Map Section ... 34 Change to JESD204B Link Control 1 (Address 0x5F) Section ... 40 Changes to Register 0x3A ... 36
Changes to Register 0x6F, Register 0x70, Register 0x72,
9/2015—Rev. B to Rev. C
Register 0x73, Register 0x74, Register 0x75 .. 38 Changes to General Description Section .. 3 Changes to JESD204B Link Control 2 (Address 0x60) Section ... 40 Changes to Nyquist Clock Input Options Section ... 21 Changes to JESD204B Overview Section .. 24
2/2014—Rev. 0 to Rev. A
Changes to Figure 60 .. 27 Changes to Data Output Parameters, Table 4 .. 8 Change to Table 17 ... 37 Changes to Figure 3 ... 9
5/2014—Rev. A to Rev. B 4/2013—Revision 0: Initial Version
Changed Minimum RF Clock Rate from 625 MHz to 500 MHz (Throughout) .. 6 Rev. D | Page 2 of 44 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY PRODUCT HIGHLIGHTS SPECIFICATIONS ADC DC SPECIFICATIONS ADC AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS EQUIVALENT CIRCUITS THEORY OF OPERATION ADC ARCHITECTURE ANALOG INPUT CONSIDERATIONS Input Common Mode Differential Input Configurations VOLTAGE REFERENCE CLOCK INPUT CONSIDERATIONS Nyquist Clock Input Options RF Clock Input Options Input Clock Divider Clock Duty Cycle Jitter Considerations POWER DISSIPATION AND STANDBY MODE DIGITAL OUTPUTS JESD204B TRANSMIT TOP LEVEL DESCRIPTION JESD204B Overview JESD204B Synchronization Details CGS Phase ILAS Phase Data Transmission Phase Link Setup Parameters Disable Lane Before Changing Configuration Configure Detailed Options Check FCHK, Checksum of JESD204B Interface Parameters Set Additional Digital Output Configuration Options Reenable Lane After Configuration Frame and Lane Alignment Monitoring and Correction Digital Outputs and Timing ADC OVERRANGE AND GAIN CONTROL ADC Overrange (OR) Gain Switching Fast Threshold Detection (FD) DC CORRECTION (DCC) DC CORRECTION BANDWIDTH DC CORRECTION READBACK DC CORRECTION FREEZE DC CORRECTION ENABLE BITS SERIAL PORT INTERFACE (SPI) CONFIGURATION USING THE SPI HARDWARE INTERFACE SPI ACCESSIBLE FEATURES MEMORY MAP READING THE MEMORY MAP REGISTER TABLE Open and Reserved Locations Default Values Logic Levels Transfer Register Map MEMORY MAP REGISTER TABLE MEMORY MAP REGISTER DESCRIPTIONS PDWN Modes (Address 0x08) Output Mode (Address 0x14) SYNCINB±/SYSREF± Control (Address 0x3A) DC Correction Control (Address 0x40) DC Correction Value 0 (Address 0x41) DC Correction Value 1 (Address 0x42) Fast Detect Control (Address 0x45) Fast Detect Upper Threshold (Address 0x47 and Address 0x48) Fast Detect Lower Threshold (Address 0x49 and Address 0x4A) Fast Detect Dwell Time (Address 0x4B and Address 0x4C) JESD204B Quick Configuration (Address 0x5E) JESD204B Link Control 1 (Address 0x5F) JESD204B Link Control 2 (Address 0x60) JESD204B Link Control 3 (Address 0x61) JESD204B Device Identification (DID) Configuration (Address 0x64) JESD204B Bank Identification (BID) Configuration (Address 0x65) JESD204B Lane Identification (LID) Configuration (Address 0x67) JESD204B Scrambler (SCR) and Lane (L) Configuration (Address 0x6E) JESD204B Parameter, F (Address 0x6F, Read Only) JESD204B Parameter, K (Address 0x70) JESD204B Parameter, M (Address 0x71) JESD204B Parameters, N/CS (Address 0x72) JESD204B Parameter, Subclass/N’ (Address 0x73) JESD204B Samples per Converter per Frame Cycle (S) (Address 0x74) JESD204B Parameters HD and CF (Address 0x75) JESD204B Reserved 1 (Address 0x76) JESD204B Reserved 2 (Address 0x77) JESD204B Checksum (Address 0x79) JESD204B Output Driver Control (Address 0x80) JESD204B LMFC Offset (Address 0x8B) JESD204B Preemphasis (Address 0xA8) APPLICATIONS INFORMATION DESIGN GUIDELINES Power and Ground Recommendations Exposed Pad Thermal Heat Slug Recommendations VCM SPI Port OUTLINE DIMENSIONS ORDERING GUIDE
AD9683 Data Sheet TABLE OF CONTENTS
Features .. 1 Power Dissipation and Standby Mode .. 23 Applications ... 1 Digital Outputs ... 24 Functional Block Diagram .. 1 JESD204B Transmit Top Level Description .. 24 General Description ... 1 ADC Overrange and Gain Control .. 29 Revision History ... 2 DC Correction (DCC) ... 31 Product Highlights ... 3 DC Correction Bandwidth .. 31 Specifications ... 4 DC Correction Readback .. 31 ADC DC Specifications ... 4 DC Correction Freeze .. 31 ADC AC Specifications ... 5 DC Correction Enable Bits ... 31 Digital Specifications ... 6 Serial Port Interface (SPI) .. 32 Switching Specifications .. 8 Configuration Using the SPI ... 32 Timing Specifications .. 9 Hardware Interface ... 32 Absolute Maximum Ratings .. 10 SPI Accessible Features .. 33 Thermal Characteristics .. 10 Memory Map .. 34 ESD Caution .. 10 Reading the Memory Map Register Table ... 34 Pin Configuration and Function Descriptions ... 11 Memory Map Register Table ... 35 Typical Performance Characteristics ... 13 Memory Map Register Descriptions .. 39 Equivalent Circuits ... 18 Applications Information .. 43 Theory of Operation .. 19 Design Guidelines .. 43 ADC Architecture .. 19 Outline Dimensions ... 44 Analog Input Considerations .. 19 Ordering Guide .. 44 Voltage Reference ... 20 Clock Input Considerations .. 21
REVISION HISTORY 6/2016—Rev. C to Rev.D
Changes to SYNCINB+ Pin Description .. 11 Changes to Table 17 .. 37 Changes to Transfer Register Map Section ... 34 Change to JESD204B Link Control 1 (Address 0x5F) Section ... 40 Changes to Register 0x3A ... 36
Changes to Register 0x6F, Register 0x70, Register 0x72,
9/2015—Rev. B to Rev. C
Register 0x73, Register 0x74, Register 0x75 .. 38 Changes to General Description Section .. 3 Changes to JESD204B Link Control 2 (Address 0x60) Section ... 40 Changes to Nyquist Clock Input Options Section ... 21 Changes to JESD204B Overview Section .. 24
2/2014—Rev. 0 to Rev. A
Changes to Figure 60 .. 27 Changes to Data Output Parameters, Table 4 .. 8 Change to Table 17 ... 37 Changes to Figure 3 ... 9
5/2014—Rev. A to Rev. B 4/2013—Revision 0: Initial Version
Changed Minimum RF Clock Rate from 625 MHz to 500 MHz (Throughout) .. 6 Rev. D | Page 2 of 44 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY PRODUCT HIGHLIGHTS SPECIFICATIONS ADC DC SPECIFICATIONS ADC AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS EQUIVALENT CIRCUITS THEORY OF OPERATION ADC ARCHITECTURE ANALOG INPUT CONSIDERATIONS Input Common Mode Differential Input Configurations VOLTAGE REFERENCE CLOCK INPUT CONSIDERATIONS Nyquist Clock Input Options RF Clock Input Options Input Clock Divider Clock Duty Cycle Jitter Considerations POWER DISSIPATION AND STANDBY MODE DIGITAL OUTPUTS JESD204B TRANSMIT TOP LEVEL DESCRIPTION JESD204B Overview JESD204B Synchronization Details CGS Phase ILAS Phase Data Transmission Phase Link Setup Parameters Disable Lane Before Changing Configuration Configure Detailed Options Check FCHK, Checksum of JESD204B Interface Parameters Set Additional Digital Output Configuration Options Reenable Lane After Configuration Frame and Lane Alignment Monitoring and Correction Digital Outputs and Timing ADC OVERRANGE AND GAIN CONTROL ADC Overrange (OR) Gain Switching Fast Threshold Detection (FD) DC CORRECTION (DCC) DC CORRECTION BANDWIDTH DC CORRECTION READBACK DC CORRECTION FREEZE DC CORRECTION ENABLE BITS SERIAL PORT INTERFACE (SPI) CONFIGURATION USING THE SPI HARDWARE INTERFACE SPI ACCESSIBLE FEATURES MEMORY MAP READING THE MEMORY MAP REGISTER TABLE Open and Reserved Locations Default Values Logic Levels Transfer Register Map MEMORY MAP REGISTER TABLE MEMORY MAP REGISTER DESCRIPTIONS PDWN Modes (Address 0x08) Output Mode (Address 0x14) SYNCINB±/SYSREF± Control (Address 0x3A) DC Correction Control (Address 0x40) DC Correction Value 0 (Address 0x41) DC Correction Value 1 (Address 0x42) Fast Detect Control (Address 0x45) Fast Detect Upper Threshold (Address 0x47 and Address 0x48) Fast Detect Lower Threshold (Address 0x49 and Address 0x4A) Fast Detect Dwell Time (Address 0x4B and Address 0x4C) JESD204B Quick Configuration (Address 0x5E) JESD204B Link Control 1 (Address 0x5F) JESD204B Link Control 2 (Address 0x60) JESD204B Link Control 3 (Address 0x61) JESD204B Device Identification (DID) Configuration (Address 0x64) JESD204B Bank Identification (BID) Configuration (Address 0x65) JESD204B Lane Identification (LID) Configuration (Address 0x67) JESD204B Scrambler (SCR) and Lane (L) Configuration (Address 0x6E) JESD204B Parameter, F (Address 0x6F, Read Only) JESD204B Parameter, K (Address 0x70) JESD204B Parameter, M (Address 0x71) JESD204B Parameters, N/CS (Address 0x72) JESD204B Parameter, Subclass/N’ (Address 0x73) JESD204B Samples per Converter per Frame Cycle (S) (Address 0x74) JESD204B Parameters HD and CF (Address 0x75) JESD204B Reserved 1 (Address 0x76) JESD204B Reserved 2 (Address 0x77) JESD204B Checksum (Address 0x79) JESD204B Output Driver Control (Address 0x80) JESD204B LMFC Offset (Address 0x8B) JESD204B Preemphasis (Address 0xA8) APPLICATIONS INFORMATION DESIGN GUIDELINES Power and Ground Recommendations Exposed Pad Thermal Heat Slug Recommendations VCM SPI Port OUTLINE DIMENSIONS ORDERING GUIDE