Datasheet AD7175-8 (Analog Devices) - 54

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Data Sheet AD7175-8 INTERFACE MODE REGISTER Address: 0x02, Reset: 0x0000, Name: IFMODE
The interface mode register configures various serial interface options.
Table 28. Bit Descriptions for IFMODE Bits Bit Name Settings Description Reset Access
[15:13] RESERVED These bits are reserved; set these bits to 0. 0x0 R 12 ALT_SYNC This bit enables a different behavior of the SYNC pin to allow the use 0x0 RW of SYNC as a control for conversions when cycling channels (see the description of the SYNC_EN bit in the GPIO Configuration Register section for details). 0 Disabled 1 Enabled 11 IOSTRENGTH This bit controls the drive strength of the DOUT/RDY pin. Set this bit when 0x0 RW reading from the serial interface at high speed with a low IOVDD supply and moderate capacitance. 0 Disabled (default) 1 Enabled [10:9] RESERVED These bits are reserved; set these bits to 0. 0x0 R 8 DOUT_RESET See the DOUT_RESET section for more information. 0x0 RW 0 Disabled 1 Enabled 7 CONTREAD This bit enables the continuous read mode of the ADC data register. The 0x0 RW ADC must be configured in continuous conversion mode to use continuous read mode. For more details, see the Operating Modes section. 0 Disabled 1 Enabled 6 DATA_STAT This bit enables the status register to be appended to the data register 0x0 RW when read so that channel and status information are transmitted with the data. This is the only way to be sure that the channel bits read from the status register correspond to the data in the data register. 0 Disabled 1 Enabled 5 REG_CHECK This bit enables a register integrity checker, which can be used to monitor 0x0 RW any change in the value of the user registers. To use this feature, configure all other registers as desired with this bit cleared. Then write to this register to set the REG_CHECK bit to 1. If the contents of any of the registers change, the REG_ERROR bit is set in the status register. To clear the error, set the REG_CHECK bit to 0. Neither the interface mode register nor the ADC data or status registers are included in the registers that are checked. If a register must have a new value written, this bit must first be cleared; otherwise, an error is flagged when the new register contents are written. 0 Disabled 1 Enabled 4 RESERVED This bit is reserved; set this bit to 0. 0x0 R [3:2] CRC_EN These bits enable CRC protection of register reads/writes. CRC increases 0x00 RW the number of bytes in a serial interface transfer by one. See the CRC Calculation section for more details. 00 Disabled 01 XOR checksum enabled for register read transactions; register writes still use CRC with these bits set 10 CRC checksum enabled for read and write transactions 1 RESERVED This bit is reserved; set this bit to 0. 0x0 R Rev. 0 | Page 53 of 64 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING CHARACTERISTICS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS NOISE PERFORMANCE AND RESOLUTION GETTING STARTED POWER SUPPLIES DIGITAL COMMUNICATION Accessing the ADC Register Map AD7175-8 RESET CONFIGURATION OVERVIEW Channel Configuration Channel Registers ADC Setups Setup Configuration Registers Filter Configuration Registers Gain Registers Offset Registers ADC Mode and Interface Mode Configuration ADC Mode Register Interface Mode Register Understanding Configuration Flexibility CIRCUIT DESCRIPTION BUFFERED ANALOG INPUT CROSSPOINT MULTIPLEXER Fully Differential Inputs Single-Ended Inputs AD7175-8 REFERENCE External Reference Internal Reference BUFFERED REFERENCE INPUT CLOCK SOURCE Internal Oscillator External Crystal External Clock DIGITAL FILTERS SINC5 + SINC1 FILTER SINC3 FILTER SINGLE CYCLE SETTLING ENHANCED 50 HZ AND 60 HZ REJECTION FILTERS OPERATING MODES CONTINUOUS CONVERSION MODE CONTINUOUS READ MODE SINGLE CONVERSION MODE STANDBY AND POWER-DOWN MODES CALIBRATION DIGITAL INTERFACE CHECKSUM PROTECTION CRC CALCULATION Polynomial Example of a Polynomial CRC Calculation—24-Bit Word: 0x654321 (Eight Command Bits and 16-Bit Data) XOR Calculation Example of an XOR Calculation—24-Bit Word: 0x654321 (Eight Command Bits and 16-Bit Data) INTEGRATED FUNCTIONS GENERAL-PURPOSE I/O EXTERNAL MULTIPLEXER CONTROL DELAY 16-BIT/24-BIT CONVERSIONS DOUT_RESET SYNCHRONIZATION Normal Synchronization Alternate Synchronization ERROR FLAGS ADC_ERROR CRC_ERROR REG_ERROR Input/Output DATA_STAT IOSTRENGTH POWER-DOWN SWITCH INTERNAL TEMPERATURE SENSOR GROUNDING AND LAYOUT REGISTER SUMMARY REGISTER DETAILS COMMUNICATIONS REGISTER STATUS REGISTER ADC MODE REGISTER INTERFACE MODE REGISTER REGISTER CHECK DATA REGISTER GPIO CONFIGURATION REGISTER ID REGISTER CHANNEL REGISTER 0 CHANNEL REGISTER 1 TO CHANNEL REGISTER 15 SETUP CONFIGURATION REGISTER 0 SETUP CONFIGURATION REGISTER 1 TO SETUP CONFIGURATION REGISTER 7 FILTER CONFIGURATION REGISTER 0 FILTER CONFIGURATION REGISTER 1 TO FILTER CONFIGURATION REGISTER 7 OFFSET REGISTER 0 OFFSET REGISTER 1 TO OFFSET REGISTER 7 GAIN REGISTER 0 GAIN REGISTER 1 TO GAIN REGISTER 7 OUTLINE DIMENSIONS ORDERING GUIDE