Datasheet AD9634 (Analog Devices) - 4

FabricanteAnalog Devices
Descripción12-Bit, 170 MSPS/210 MSPS/250 MSPS, 1.8 V Analog-to-Digital Converter
Páginas / Página31 / 4 — Data Sheet. AD9634. SPECIFICATIONS ADC DC SPECIFICATIONS. Table 1. …
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Data Sheet. AD9634. SPECIFICATIONS ADC DC SPECIFICATIONS. Table 1. AD9634-170. AD9634-210. AD9634-250. Parameter. Temperature. Min. Typ. Max

Data Sheet AD9634 SPECIFICATIONS ADC DC SPECIFICATIONS Table 1 AD9634-170 AD9634-210 AD9634-250 Parameter Temperature Min Typ Max

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Data Sheet AD9634 SPECIFICATIONS ADC DC SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.75 V p-p ful scale input range, DCS enabled, unless otherwise noted.
Table 1. AD9634-170 AD9634-210 AD9634-250 Parameter Temperature Min Typ Max Min Typ Max Min Typ Max Unit
RESOLUTION Full 12 12 12 Bits ACCURACY No Missing Codes Full Guaranteed Guaranteed Guaranteed Offset Error Full ±11 ±11 ±11 mV Gain Error Full +2/−11 +1/−8 +3/−7 %FSR Differential Nonlinearity (DNL) Full ±0.4 ±0.4 ±0.4 LSB 25°C ±0.22 ±0.22 ±0.22 LSB Integral Nonlinearity (INL)1 Full ±0.4 ±0.4 ±0.6 LSB 25°C ±0.2 ±0.2 ±0.27 LSB TEMPERATURE DRIFT Offset Error Full ±7 ±7 ±7 ppm/°C Gain Error Full ±55 ±58 ±75 ppm/°C INPUT REFERRED NOISE VREF = 1.0 V 25°C 0.531 0.391 0.407 LSB rms ANALOG INPUT Input Span Full 1.75 1.75 1.75 V p-p Input Capacitance2 Full 2.5 2.5 2.5 pF Input Resistance3 Full 20 20 20 kΩ Input Common-Mode Voltage Full 0.9 0.9 0.9 V POWER SUPPLIES Supply Voltage AVDD Full 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V DRVDD Full 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V Supply Current I 1 AVDD Full 123 134 129 139 136 145 mA I 1 DRVDD Full 50 54 56 60 64 68 mA POWER CONSUMPTION Sine Wave Input (DRVDD = 1.8 V) Full 311 340 333 360 360 385 mW Standby Power4 Full 50 50 50 mW Power-Down Power Full 5 5 5 mW 1 Measured with a low input frequency, full-scale sine wave. 2 Input capacitance refers to the effective capacitance between one differential input pin and its complement. 3 Input resistance refers to the effective resistance between one differential input pin and its complement. 4 Standby power is measured with a dc input and the CLK pin inactive (that is, set to AVDD or AGND). Rev. B | Page 3 of 30 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ADC DC SPECIFICATIONS ADC AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS Timing Diagram TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS EQUIVALENT CIRCUITS THEORY OF OPERATION ADC ARCHITECTURE ANALOG INPUT CONSIDERATIONS Input Common Mode Differential Input Configurations VOLTAGE REFERENCE CLOCK INPUT CONSIDERATIONS Clock Input Options Input Clock Divider Clock Duty Cycle Jitter Considerations POWER DISSIPATION AND STANDBY MODE DIGITAL OUTPUTS Digital Output Enable Function (OEB) Timing Data Clock Output (DCO) ADC OVERRANGE (OR) SERIAL PORT INTERFACE (SPI) CONFIGURATION USING THE SPI HARDWARE INTERFACE SPI ACCESSIBLE FEATURES MEMORY MAP READING THE MEMORY MAP REGISTER TABLE Open Locations Default Values Logic Levels Transfer Register Map MEMORY MAP REGISTER TABLE APPLICATIONS INFORMATION DESIGN GUIDELINES Power and Ground Recommendations Exposed Paddle Thermal Heat Slug Recommendations VCM SPI Port OUTLINE DIMENSIONS ORDERING GUIDE