Datasheet AD9261 (Analog Devices)

16-Bit, 10 MHz Bandwidth, 30 MSPS to 160 MSPS Continuous Time Sigma-Delta ADC AD9261 FEATURES FUNCTIONAL BLOCK DIAGRAM SNR: 83 dB (85 dBFS) to 10 MHz input AVDD DRVDD SFDR: 87 dBc to 10 MHz input OR Noise figure: 15 dB VIN+ Σ-Δ LOW-PASS SAMPLE D15 CMOS DECIMATION RATE Input impedance: 1 kΩ MODULATOR BUFFER VIN– FILTER CONVERTER D0 Power: 340 mW PLL_ 1.8 V analog supply operation LOCKED 1.8 V to 3.3 V output supply PHASE CLK+ VREF LOCKED AD9261 Selectable bandwidth LOOP CLK– 2.5 MHz/5 MHz/10 MHz SERIAL DCO Output data rate: 30 MSPS to 160 MSPS CFILT INTERFACE
1
Integrated decimation filters
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Integrated sample rate converter AGND SDIO SCLK CSB DGND
07 Figure 1.
On-chip PLL clock multiplier On-chip voltage reference Offset binary, Gray code, or twos complement data format Serial control interface (SPI) APPLICATIONS Data acquisition Automated test equipment Instrumentation Medical imaging GENERAL DESCRIPTION
The AD9261 is a single 16-bit analog-to-digital converter The digital output data is presented in offset binary, Gray code, (ADC) based on a continuous time (CT) sigma-delta (Σ-Δ) or twos complement format. A data clock output (DCO) is architecture that achieves 87 dBc of dynamic range over a 10 MHz provided to ensure proper timing with the receiving logic. input bandwidth. The integrated features and characteristics The AD9261 operates on a 1.8 V analog supply and a 1.8 V unique to the continuous time Σ-Δ architecture significantly to 3.3 V digital supply, consuming 340 mW. The AD9261 is simplify its use and minimize the need for external components. available in a 48-lead LFCSP and is specified over the industrial The AD9261 has a resistive input impedance that relaxes the temperature range (−40°C to +85°C). requirements of the driver amplifier. In addition, a 32× oversam-
PRODUCT HIGHLIGHTS
pled fifth-order continuous time loop filter significantly attenuates 1. Continuous time Σ-Δ architecture efficiently achieves high out-of-band signals and aliases, reducing the need for external filters at the input. dynamic range and wide bandwidth. 2. Passive input structure reduces or eliminates the require- An external clock input or the integrated integer-N PLL provides ments for a driver amplifier. the 640 MHz internal clock needed for the oversampled conti- 3. An oversampling ratio of 32× and high order loop filter nuous time Σ-Δ modulator. On-chip decimation filters and sample provide excellent alias rejection reducing or eliminating the rate converters reduce the modulator data rate from 640 MSPS to a need for antialiasing filters. user-defined output data rate from 30 MSPS to 160 MSPS, 4. An integrated decimation filter, sample rate converter, PLL enabling a more efficient and direct interface. clock multiplier, and voltage reference provide ease of use. 5. This part operates from a single 1.8 V analog power supply and 1.8 V to 3.3 V output supply.
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