Datasheet AD7195 (Analog Devices) - 32

Data Sheet AD7195 Continuous Read
conversion is complete, and the new conversion is placed in Rather than write to the communications register each time the output serial register. a conversion is complete to access the data, the AD7195 can To exit the continuous read mode, Instruction 01011000 must be configured so that the conversions are placed on the be written to the communications register while the RDY pin DOUT/RDY line automatically. By writing 01011100 to is low. While in continuous read mode, the ADC monitors the communications register, the user need only apply the activity on the DIN line so that it can receive the instruction appropriate number of SCLK cycles to the ADC, and the to exit the continuous read mode. Additionally, a reset occurs conversion word is automatically placed on the DOUT/RDY if 40 consecutive 1s are seen on DIN. Therefore, DIN should line when a conversion is complete. The ADC should be be held low in continuous read mode until an instruction is to configured for continuous conversion mode. be written to the device. When DOUT/RDY goes low to indicate the end of a conversion, When several channels are enabled, the ADC continuously sufficient SCLK cycles must be applied to the ADC; the data steps through the enabled channels and performs one con- conversion is then placed on the DOUT/RDY line. When the version on each channel each time that it is selected. DOUT/ conversion is read, DOUT/RDY returns high until the next RDY pulses low when a conversion is available. When the user conversion is available. In this mode, the data can be read only applies sufficient SCLK pulses, the data is automatical y placed once. Also, the user must ensure that the data-word is read on the DOUT/RDY pin. If the DAT_STA bit in the mode before the next conversion is complete. If the user has not read register is set to 1, the contents of the status register are output the conversion before the completion of the next conversion, along with the conversion. The status register indicates the or if insufficient serial clocks are applied to the AD7195 to channel to which the conversion corresponds. read the word, the serial output register is reset when the next
CS 0x5C DIN DATA DATA DATA DOUT/RDY
031
SCLK
08771- Figure 23. Continuous Read Rev. A | Page 31 of 44 Document Outline FEATURES INTERFACE APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING CHARACTERISTICS Circuit and Timing Diagram ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS RMS NOISE AND RESOLUTION SINC4 CHOP DISABLED SINC3 CHOP DISABLED SINC4 CHOP ENABLED SINC3 CHOP ENABLED ON-CHIP REGISTERS COMMUNICATIONS REGISTER STATUS REGISTER MODE REGISTER CONFIGURATION REGISTER DATA REGISTER ID REGISTER GPOCON REGISTER OFFSET REGISTER FULL-SCALE REGISTER ADC CIRCUIT INFORMATION OVERVIEW Analog Inputs Multiplexer PGA Reference Detect Burnout Currents Σ-Δ ADC and Filter AC Excitation Serial Interface Clock Temperature Sensor Calibration ANALOG INPUT CHANNEL PGA REFERENCE REFERENCE DETECT BIPOLAR/UNIPOLAR CONFIGURATION DATA OUTPUT CODING BURNOUT CURRENTS AC EXCITATION CHANNEL SEQUENCER Single Conversion Mode Continuous Conversion Mode Continuous Read RESET SYSTEM SYNCHRONIZATION CLOCK ENABLE PARITY TEMPERATURE SENSOR BRIDGE POWER-DOWN SWITCH CALIBRATION DIGITAL FILTER SINC4 FILTER (CHOP DISABLED) Sinc4 Output Data Rate/Settling Time Sinc4 Zero Latency Sinc4 50 Hz/60 Hz Rejection SINC3 FILTER (CHOP DISABLED) Sinc3 Output Data Rate and Settling Time Sinc3 Zero Latency Sinc3 50 Hz/60 Hz Rejection CHOP ENABLED (SINC4 FILTER) Output Data Rate and Settling Time (Sinc4 Chop Enabled) 50 Hz/60 Hz Rejection (Sinc4 Chop Enabled) CHOP ENABLED (SINC3 FILTER) Output Data Rate and Settling Time (Sinc3 Chop Enabled) 50 Hz/60 Hz Rejection (Sinc3 Chop Enabled) SUMMARY OF FILTER OPTIONS GROUNDING AND LAYOUT APPLICATIONS INFORMATION WEIGH SCALES OUTLINE DIMENSIONS ORDERING GUIDE