Datasheet AD9267 (Analog Devices)

10 MHz Bandwidth, 640 MSPS Dual Continuous Time Sigma-Delta Modulator AD9267 FEATURES FUNCTIONAL BLOCK DIAGRAM SNR: 83 dB (85 dBFS) to 10 MHz input AVDD PDWNB PDWNA DRVDD SFDR: −88 dBc to 10 MHz input OR±A Noise figure: 15 dB VIN+A Σ D3±A -Δ S RS E Input impedance: 1 kΩ D V MODULATOR VIN–A LV Power: 416 mW DRI D0±A PLL_LOCKED 10 MHz real or 20 MHz complex bandwidth AD9267 PLLMULT4 1.8 V analog supply operation PLLMULT3 On-chip PLL clock multiplier PLLMULT2 On-chip voltage reference CLK+ VREF PHASE- LOCKED Twos complement data format LOOP CLK– CFILT 640 MSPS, 4-bit LVDS data output DCO± Serial control interface (SPI) VIN–B Σ D3±B -Δ S RS D E MODULATOR IV LV APPLICATIONS VIN+B DR D0±B Baseband quadrature receivers: CDMA2000, W-CDMA, SERIAL OR±B INTERFACE multicarrier GSM/EDGE, 802.16x, and LTE
1
Quadrature sampling instrumentation
00 3-
AGND SDIO/ SCLK/ CSB DGND
77
PLLMULT1 PLLMULT0
07
GENERAL DESCRIPTION
Figure 1. The AD9267 is a dual continuous time (CT) sigma-delta (Σ-Δ) The AD9267 operates on a 1.8 V power supply, consuming modulator with −88 dBc of dynamic range over 10 MHz real 416 mW. The AD9267 is available in a 64-lead LFCSP and or 20 MHz complex bandwidth. The combination of high is specified over the industrial temperature range (−40°C dynamic range, wide bandwidth, and characteristics unique to +85°C). to the continuous time Σ-Δ modulator architecture makes the AD9267 an ideal solution for wireless communication systems.
PRODUCT HIGHLIGHTS
The AD9267 has a resistive input impedance that significantly 1. Continuous time Σ-Δ architecture efficiently achieves high relaxes the requirements of the driver amplifier. In addition, a dynamic range and wide bandwidth. 32× oversampled fifth-order continuous time loop filter attenuates 2. Passive input structure reduces or eliminates the require- out-of-band signals and aliases, reducing the need for external ments for a driver amplifier. filters at the input. The low noise figure of 15 dB relaxes the 3. An oversampling ratio of 32× and high order loop filter linearity requirements of the front-end signal chain components, provide excellent alias rejection, reducing or eliminating and the high dynamic range reduces the need for an automatic the need for antialiasing filters. gain control (AGC) loop. 4. Operates from a single 1.8 V power supply. 5. A standard serial port interface (SPI) supports various A differential input clock controls all internal conversion cycles. product features and functions. An external clock input or the integrated integer-N PLL provides 6. Features a low pin count, high speed LVDS interface with the 640 MHz internal clock needed for the oversampled conti- data output clock. nuous time Σ-Δ modulator. The digital output data is presented as 4-bit, LVDS at 640 MSPS in twos complement format. A data clock output (DCO) is provided to ensure proper latch timing with receiving logic. Additional digital signal processing may be required on the 4-bit modulator output to remove the out-of-band noise and to reduce the sample rate.
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