Datasheet AD9600 (Analog Devices) - 70

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AD9600 BILL OF MATERIALS Table 23. Evaluation Board Bill of Materials (BOM)1, 2 Reference Item Qty Designator Description Package Manufacturer Mfg. Part Number
1 1 AD9600CE_REVB PCB PCB Analog Devices 2 55 C1 to C3, C6, C7, 0.1 μF, 16 V ceramic C0402SM Murata GRM155R71C104KA88D C13, C14, C17, C18, capacitor, SMT 0402 C20 to C26, C32, C57 to C61, C65 to C76, C81 to C83, C96 to C101, C103, C105, C107, C108, C110 to C116, C145 3 1 C80 18 pF, COG, 50 V, 5% ceramic C0402SM Murata GJM1555C1H180JB01J capacitor, SMT 0402 4 2 C5, C84 4.7 pF, COG, 50 V, 5% ceramic C0402SM Murata GJM1555C1H4R7CB01J capacitor, SMT 0402 5 10 C33, C35, C63, 0.001 μF, X7R, 25 V, 10% C0402SM Murata GRM155R71H102KA01D C93 to C95, C122, ceramic capacitor, SMT 0402 C126, C127, C137 6 13 C15, C42 to C45, 1 μF, X5R, 25 V, 10% ceramic C0805 Murata GR4M219R61A105KC01D C129 to C136 capacitor, SMT 0805 7 10 C27, C41, C52 to 10 μF, X5R, 10 V, 10% ceramic C1206 Murata GRM31CR61C106KC31L C54, C62, C102, capacitor, SMT 1206 C118, C119, C124 8 1 CR5 Schottky diode HSMS2822, SOT23 SOT23 Avago Technologies HSMS-2822-BLKG 9 2 CR6, CR9 LED RED, SMT, 0603, SS-type LED0603 Panasonic LNJ208R8ARA 10 4 CR7, CR10 to CR12 50 V, 2 A diode DO_214AA Micro Commercial Components S2A-TP 11 1 CR8 30 V, 3 A diode DO_214AB Micro Commercial Components SK33-TP 12 1 F1 EMI filter FLTHMURATABNX01 Murata BNX016-01 13 1 F2 6.0 V, 3.0 A, trip current L1206 Tyco Raychem NANOSMDC150F-2 resettable fuse 14 2 J1 to J2 3-pin, male, single row, HDR3 Samtec TWS-1003-08-G-S straight header 15 9 J4 to J9, J18, J19, 2-pin, male, straight header HDR2 Samtec TWS-102-08-G-S J21 16 3 J10 to J12 Interface connector TYCO_HM_ZD Tyco 6469169-1 17 1 J14 8-pin, male, double row, CNBERG2X4H350LD Samtec TSW-104-08-T-D straight header 18 1 J16 DC power jack connector PWR_JACK1 Cui Stack PJ-002A 19 10 L1, L3, L4, L6, L8 10 μH, 2 A bead core, 1210 1210 Panasonic EXC-CL3225U1 to L13 20 1 P3 6-terminal connector PTMICRO6 Weiland Electric, Inc. Z5.531.3625.0 21 1 P4 4-terminal connector PTMICRO4 Weiland Electric, Inc. Z5.531.3425.0 22 3 R7, R30, R45 57.6 Ω, 0603, 1/10 W, R0603 NIC Components NRC06F57R6TRF 1% resistor 23 27 R2, R3, R4, R32, 0 Ω, 1/16 W, 5% resistor R0402SM NIC Components NRC04ZOTRF R33, R42, R64, R67, R69, R90, R96, R99, R101, R104, R110 to R113, R115, R119, R121, R123, R141 to R145 24 2 R13, R25 140 kΩ, 0603, 1/10 W, R0603 NIC Components NRC06F1403TRF 1% resistor 25 2 R14, R15 78.7 kΩ, 0603, 1/10 W, R0603 NIC Components NRC06F7872TRF 1% resistor Rev. B | Page 69 of 72 Document Outline FEATURES APPLICATIONS PRODUCT HIGHLIGHTS FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY GENERAL DESCRIPTION SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING CHARACTERISTICS TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS EQUIVALENT CIRCUITS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION ADC ARCHITECTURE ANALOG INPUT CONSIDERATIONS Input Common Mode Differential Input Configurations Single-Ended Input Configuration VOLTAGE REFERENCE Internal Reference Connection External Reference Operation CLOCK INPUT CONSIDERATIONS Clock Input Options Input Clock Divider Clock Duty Cycle Jitter Considerations POWER DISSIPATION AND STANDBY MODE DIGITAL OUTPUTS Digital Output Enable Function (OEB) TIMING Data Clock Output (DCO) ADC OVERRANGE AND GAIN CONTROL FAST DETECT OVERVIEW ADC FAST MAGNITUDE ADC OVERRANGE (OR) GAIN SWITCHING Coarse Upper Threshold (C_UT) Fine Upper Threshold (F_UT) Fine Lower Threshold (F_LT) Increment Gain (IG) and Decrement Gain (DG) SIGNAL MONITOR PEAK DETECTOR MODE RMS/MS MAGNITUDE MODE THRESHOLD CROSSING MODE ADDITIONAL CONTROL BITS Signal Monitor Enable Bit Complex Power Calculation Mode Enable Bit DC CORRECTION DC Correction Bandwidth DC Correction Readback DC Correction Freeze DC Correction Enable Bits SIGNAL MONITOR SPORT OUTPUT SMI SCLK SMI SDFS SMI SDO BUILT-IN SELF-TEST (BIST) AND OUTPUT TEST BUILT-IN SELF-TEST (BIST) OUTPUT TEST MODES CHANNEL/CHIP SYNCHRONIZATION SERIAL PORT INTERFACE (SPI) CONFIGURATION USING THE SPI HARDWARE INTERFACE CONFIGURATION WITHOUT THE SPI SPI ACCESSIBLE FEATURES MEMORY MAP READING THE MEMORY MAP TABLE Open Locations Default Values Logic Levels Transfer Register Map Channel-Specific Registers MEMORY MAP MEMORY MAP REGISTER DESCRIPTION Sync Control (Register 0x100) Bit 7—Signal Monitor Sync Enable Bits [6:3]—Reserved Bit 2—Clock Divider Next Sync Only Bit 1—Clock Divider Sync Enable Bit 0—Master Sync Enable Fast Detect Control (Register 0x104) Bits [7:4]—Reserved Bits [3:1]—Fast Detect Mode Select Bit 0—Fast Detect Enable Coarse Upper Threshold (Register 0x105) Bits [7:3]—Reserved Bits [2:0]—Coarse Upper Threshold Fine Upper Threshold (Register 0x106 and Register 0x107) Register 0x106, Bits [7:0]—Fine Upper Threshold [7:0] Register 0x107, Bits [7:5]—Reserved Register 0x107, Bits [4:0]—Fine Upper Threshold [12:8] Fine Lower Threshold (Register 0x108 and Register 0x109) Register 0x108, Bits [7:0]—Fine Lower Threshold [7:0]Register 0x109, Bits [7:5]—ReservedRegister 0x109, Bits [4:0]—Fine Lower Threshold [12:8] Increase Gain Dwell Time (Register 0x10A andRegister 0x10B) Register 0x10A, Bits [7:0]—Increase Gain Dwell Time [7:0]Register 0x10B, Bits [7:0]—Increase Gain Dwell Time [15:8] Signal Monitor DC Correction Control (Register 0x10C) Bit 7—ReservedBit 6—DC Correction Freeze Bits [5:2]—DC Correction Bandwidth Bit 1—DC Correction for Signal Path Enable Bit 0—DC Correction for Signal Monitor Enable Signal Monitor DC Value Channel A (Register 0x10D and Register 0x10E) Register 0x10D, Bits [7:0]—DC Value Channel A [7:0] Register 0x10E, Bits [7:6]—Reserved Register 0x10E, Bits [5:0]—DC Value Channel A [13:8] Signal Monitor DC Value Channel B (Register 0x10F and Register 0x110) Register 0x10F Bits [7:0]—DC Value Channel B [7:0] Register 0x110 Bits [7:6]—Reserved Register 0x110 Bits [5:0]—DC Value Channel B [13:8] Signal Monitor SPORT Control (Register 0x111) Bit 7—Reserved Bit 6—RMS/MS Magnitude Output Enable Bit 5—Peak Detector Output Enable Bit 4—Threshold Crossing Output Enable Bits [3:2]—SPORT SMI SCLK Divide Bit 1— SPORT SMI SCLK Sleep Bit 0—Signal Monitor SPORT Output Enable Signal Monitor Control (Register 0x112) Bit 7—Complex Power Calculation Mode Enable Bits [6:4]—Reserved Bit 3—Signal Monitor RMS/MS Select Bits [2:1]—Signal Monitor Mode Bit 0—Signal Monitor Enable Signal Monitor Period (Register 0x113 to Register 0x115) Register 0x113, Bits [7:0]—Signal Monitor Period [7:0] Register 0x114, Bits [7:0]—Signal Monitor Period [15:8] Register 0x115, Bits [7:0]—Signal Monitor Period [23:16] Signal Monitor Result Channel A (Register 0x116 to Register 0x118) Register 0x116, Bits [7:0]—Signal Monitor Result Channel A [7:0] Register 0x117, Bits [7:0]—Signal Monitor Result Channel A [15:8] Register 0x118, Bits [7:4]—Reserved Register 0x118, Bits [3:0]—Signal Monitor Result Channel A [19:16] Signal Monitor Result Channel B (Register 0x119 to Register 0x11B) Register 0x119, Bits [7:0]— Signal Monitor Result Channel B [7:0] Register 0x11A, Bits [7:0]—Signal Monitor Result Channel B [15:8] Register 0x11B, Bits [7:4]—Reserved Register 0x11B, Bits [3:0]—Signal Monitor Result Channel B [19:16] APPLICATIONS INFORMATION DESIGN GUIDELINES Power and Ground Recommendations Exposed Paddle Thermal Heat Slug Recommendations CML RBIAS Reference Decoupling SPI Port EVALUATION BOARD POWER SUPPLIES INPUT SIGNALS OUTPUT SIGNALS DEFAULT OPERATION AND JUMPER SELECTION SETTINGS POWER VIN RBIAS CLOCK PDWN CSB SCLK/DFS SDIO/DCS ALTERNATIVE CLOCK CONFIGURATIONS ALTERNATIVE ANALOG INPUT DRIVE CONFIGURATION SCHEMATICS EVALUATION BOARD LAYOUTS BILL OF MATERIALS OUTLINE DIMENSIONS ORDERING GUIDE