Datasheet AD9252 (Analog Devices) - 19

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AD9252 Data Sheet ADT1-1WT
For best dynamic performance, the source impedances driving
1:1 Z RATIO C R
VIN + x and VIN − x should be matched such that common-mode
VIN + x
settling errors are symmetrical. These errors are reduced by the
ADC 2V p-p 49.9Ω C 1 DIFF AD9252
common-mode rejection of the ADC. An internal reference buffer
R AVDD VIN – x
creates the positive and negative reference voltages, REFT and
AGND C 1kΩ
REFB, respectively, that define the span of the ADC core. The output common mode of the reference buffer is set to midsupply,
1kΩ
and the REFT and REFB voltages and span are defined as
0.1μF
18 0 6-
1C
29 REFT = 1/2 (AVDD + VREF)
DIFF IS OPTIONAL.
06 REFB = 1/2 (AVDD − VREF) Figure 36. Differential Transformer-Coupled Configuration for Baseband Applications Span = 2 × (REFT − REFB) = 2 × VREF
2V p-p ADT1-1WT 16nH 0.1μF 16nH
It can be seen from these equations that the REFT and REFB
1:1 Z RATIO 33Ω VIN+x
voltages are symmetrical about the midsupply voltage and, by
65Ω ADC 499Ω 2.2pF 1kΩ AD9252
definition, the input span is twice the value of the VREF voltage.
16nH 33Ω VIN– x
Maximum SNR performance is achieved by setting the ADC to
AVDD
the largest span in a differential configuration. In the case of the
1kΩ
AD9252, the largest input span available is 2 V p-p. 9
1kΩ 0.1μF
-01 96
Differential Input Configurations
062 Figure 37. Differential Transformer-Coupled Configuration for IF Applications There are several ways to drive the AD9252 either actively or
Single-Ended Input Configuration
passively; however, optimum performance is achieved by driving the analog input differentially. For example, using the AD8334 A single-ended input may provide adequate performance in cost- differential driver to drive the AD9252 provides excellent perfor- sensitive applications. In this configuration, SFDR and distortion mance and a flexible interface to the ADC (see Figure 39) for performance degrade due to the large input common-mode swing. baseband applications. This configuration is commonly used If the application requires a single-ended input configuration, for medical ultrasound systems. ensure that the source impedances on each input are well matched in order to achieve the best possible performance. A full-scale input For applications where SNR is a key parameter, differential of 2 V p-p can still be applied to the ADC’s VIN + x pin while the transformer coupling is the recommended input configuration VIN − x pin is terminated. Figure 38 details a typical single- (see Figure 36 and Figure 37), because the noise performance of ended input configuration. most amplifiers is not adequate to achieve the true performance
AVDD
of the AD9252.
C
Regardless of the configuration, the value of the shunt capacitor,
1kΩ R VIN + x
C, is dependent on the input frequency and may need to be
2V p-p 49.9Ω 0.1µF 1kΩ
reduced or removed.
1 ADC AVDD CDIFF AD9252 1kΩ 25Ω R VIN – x 0.1µF 1kΩ C
0 -02
1CDIFF IS OPTIONAL.
296 06 Figure 38. Single-Ended Input Configuration
0.1μF LOP VIP 187Ω 0.1μF R 0.1μF 120nH VOH INH VIN + x 1V p-p AD8334 1.0kΩ 22pF ADC LNA VGA 374Ω C AD9252 1.0kΩ R 0.1μF LMD VIN – x VOL 187Ω 0.1μF AVDD LON VIN 0.1μF 10μF 1kΩ
1
1kΩ
-02
18nF 274Ω 0.1μF
296 06 Figure 39. Differential Input Configuration Using the AD8334 Rev. E | Page 18 of 52 Document Outline Features Applications General Description Functional Block Diagram Product Highlights Revision History Specifications AC Specifications Digital Specifications Switching Specifications Timing Diagrams Absolute Maximum Ratings Thermal Impedance ESD Caution Pin Configuration and Function Descriptions Equivalent Circuits Typical Performance Characteristics Theory of Operation Analog Input Considerations Differential Input Configurations Single-Ended Input Configuration Clock Input Considerations Clock Duty Cycle Considerations Clock Jitter Considerations Power Dissipation and Power-Down Mode Digital Outputs and Timing SDIO/ODM Pin SCLK/DTP Pin CSB Pin RBIAS Pin Voltage Reference Internal Reference Operation External Reference Operation Serial Port Interface (SPI) Hardware Interface Memory Map Reading the Memory Map Table Reserved Locations Default Values Logic Levels Applications Information Design Guidelines Power and Ground Recommendations Exposed Paddle Thermal Heat Slug Recommendations Evaluation Board Power Supplies Input Signals Output Signals Default Operation and Jumper Selection Settings Alternative Analog Input Drive Configuration Outline Dimensions Ordering Guide