Datasheet AD9222 (Analog Devices) - 6

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Data Sheet AD9222 DIGITAL SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −0.5 dBFS, unless otherwise noted.
Table 3. AD9222-40 AD9222-50 AD9222-65 Parameter
1
Temp Min Typ Max Min Typ Max Min Typ Max Unit
CLOCK INPUTS (CLK+, CLK−) Logic Compliance CMOS/LVDS/LVPECL CMOS/LVDS/LVPECL CMOS/LVDS/LVPECL Differential Input Voltage2 Full 250 250 250 mV p-p Input Common-Mode Voltage Full 1.2 1.2 1.2 V Input Resistance (Differential) 25°C 20 20 20 kΩ Input Capacitance 25°C 1.5 1.5 1.5 pF LOGIC INPUTS (PDWN, SCLK/DTP) Logic 1 Voltage Full 1.2 3.6 1.2 3.6 1.2 3.6 V Logic 0 Voltage Full 0 0.3 0.3 0.3 V Input Resistance 25°C 30 30 30 kΩ Input Capacitance 25°C 0.5 0.5 0.5 pF LOGIC INPUT (CSB) Logic 1 Voltage Full 1.2 3.6 1.2 3.6 1.2 3.6 V Logic 0 Voltage Full 0 0.3 0.3 0.3 V Input Resistance 25°C 70 70 70 kΩ Input Capacitance 25°C 0.5 0.5 0.5 pF LOGIC INPUT (SDIO/ODM) Logic 1 Voltage Full 1.2 DRVDD + 0.3 1.2 DRVDD + 0.3 1.2 DRVDD + 0.3 V Logic 0 Voltage Full 0 0.3 0 0.3 0 0.3 V Input Resistance 25°C 30 30 30 kΩ Input Capacitance 25°C 2 2 2 pF LOGIC OUTPUT (SDIO/ODM)3 Logic 1 Voltage (IOH = 800 μA) Full 1.79 1.79 1.79 V Logic 0 Voltage (IOL = 50 μA) Full 0.05 0.05 0.05 V DIGITAL OUTPUTS (D + x, D − x), (ANSI-644)1 Logic Compliance LVDS LVDS LVDS Differential Output Voltage (VOD) Full 247 454 247 454 247 454 mV Output Offset Voltage (VOS) Full 1.125 1.375 1.125 1.375 1.125 1.375 V Output Coding (Default) Offset binary Offset binary Offset binary DIGITAL OUTPUTS (D + x, D − x), (Low Power, Reduced Signal Option)1 Logic Compliance LVDS LVDS LVDS Differential Output Voltage (VOD) Full 150 250 150 250 150 250 mV Output Offset Voltage (VOS) Full 1.10 1.30 1.10 1.30 1.10 1.30 V Output Coding (Default) Offset binary Offset binary Offset binary 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed. 2 This is specified for LVDS and LVPECL only. 3 This is specified for 13 SDIO pins sharing the same connection. Rev. F | Page 5 of 60 Document Outline Features Applications General Description Functional Block Diagram Product Highlights Table of Contents Revision History Specifications AC Specifications Digital Specifications Switching Specifications Timing Diagrams Absolute Maximum Ratings Thermal Impedance ESD Caution Pin Configuration and Function Descriptions Equivalent Circuits Typical Performance Characteristics Theory of Operation Analog Input Considerations Differential Input Configurations Single-Ended Input Configuration Clock Input Considerations Clock Duty Cycle Considerations Clock Jitter Considerations Power Dissipation and Power-Down Mode Digital Outputs and Timing SDIO/ODM Pin SCLK/DTP Pin CSB Pin RBIAS Pin Voltage Reference Internal Reference Operation External Reference Operation Serial Port Interface (SPI) Hardware Interface Memory Map Reading the Memory Map Table Reserved Locations Default Values Logic Levels Power and Ground Recommendations Exposed Paddle Thermal Heat Slug Recommendations Evaluation Board Power Supplies Input Signals Output Signals Default Operation and Jumper Selection Settings Alternative Analog Input Drive Configuration Outline Dimensions Ordering Guide