Datasheet AD1555, AD1556 (Analog Devices) - 16

FabricanteAnalog Devices
DescripciónDigital Filter/Decimator for 24-Bit Sigma-Delta A/D Converter
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AD1555/AD1556. CIRCUIT DESCRIPTION. MULTIPLEXER AND PROGRAMMABLE GAIN. AMPLIFIER (PGA). Analog Inputs. AC SINE. TEST. DC TEST. SOURCE

AD1555/AD1556 CIRCUIT DESCRIPTION MULTIPLEXER AND PROGRAMMABLE GAIN AMPLIFIER (PGA) Analog Inputs AC SINE TEST DC TEST SOURCE

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AD1555/AD1556 CIRCUIT DESCRIPTION
The AD1555 operates from a dual analog supply (± 5 V), The AD1555/AD1556 chipset is a complete sigma-delta 24-bit while the digital part of the AD1555 operates from a +5 V A/D converter with very high dynamic range intended for the supply. The AD1556 operates from a single 3.3 V or 5 V measurement of low frequency signals up to a few kHz such as supply. Each device exhibits low power dissipation and can those in seismic applications. be configured for standby mode. The AD1555 contains an analog multiplexer, a fully differential Figure 7 illustrates a typical operating circuit. programmable gain amplifier and a fourth order sigma-delta modulator. The analog multiplexer allows selection of one fully
MULTIPLEXER AND PROGRAMMABLE GAIN
differential input from two different external inputs, an internal
AMPLIFIER (PGA)
ground reference or an internal full-scale voltage reference. The
Analog Inputs
fully differential programmable gain amplifier (PGA) has five gain The AD1555 has two sets of fully differential inputs AIN and settings of 1, 2.5, 8.5, 34, and 128, which allow the part to handle TIN. The common-mode rejection capability of these inputs a total of five different input ranges: 1.6 V rms, 636 mV rms, generally surpasses the performance of conventional program- 187 mV rms, 47 mV rms, and 12.4 mV rms that are programmed mable gain amplifiers. The very high input impedance, typically via digital input pins (CB0 to CB4). The modulator that operates higher than 140 MΩ, allows direct connection of the sensor to nominally at a sampling frequency of 256 kHz, outputs a bit- the AD1555 inputs, even through serial resistances. Figure 7 stream whose ones-density is proportional to its input voltage. illustrates such a configuration. The passive filter between the This bitstream can be filtered using the AD1556, which is a sensor and the AD1555 is shown here as an example. Other digital finite impulse low pass filter (FIR). The AD1556 outputs filter structures could be used, depending on the specific require- the data in a 24-bit word over a serial interface. The cutoff ments of the application. Also, the Johnson noise (√4 k TRB) of frequency and output rate of this filter can be programmed via the serial resistance should be taken into consideration. For an on-chip register or by hardware through digital input pins. instance, a 1 kΩ serial resistance reduces by approximately 1.3 dB The dynamic performance and the equivalent input noise vary the dynamic performance of a system using a gain setting of with gain and output rate as shown in Table I. The use of the 128 at an output word rate FO = 500 Hz. For applications different PGA gain settings allows enhancement of the total system where the sensor inputs must be protected against severe dynamic range up to 146 dB (gain of 34 or 128 and FO = 250 Hz).
AC SINE TEST DC TEST SOURCE SOURCE 3 UNUSED AD1555 PINS MUST BE LEFT TEM 2 UNCONNECTED; P AD780 +VIN +5V UNUSED AD1556 INPUT PINS MUST BE 3 14 6 +5V –5V V TIED TO DGND OR V OUT GND O/P L. ADG609 100nF 100nF 100nF 4 8 DB DA CLOCK SOURCE SERIAL DATA 15 15 22 F 1.024MHz INTERFACE 9 8 ADSP-21xxx OR P 32 2 28 25 23 22 16 PGAOUT MODIN REFIN REFCAP1 AGND3 CS 17 7 5 R/W TIN (+) CB0...CB4 CB0...CB4 18 8 RSEL TIN (–) 15 MFLG MFLG 30 TDATA 17 13 MDATA MDATA TO OTHER AD1555s SCLK 19 R1 R3 5 AD1555 18 DIN AIN (+) MCLK MCLK 14 +5V DOUT T C 15 1 1 SENSOR: DRDY GEOPHONE, C3 15 20 19 ERROR HYDROPHONE... VL T2 C2 6 100nF 10 F AD1556 TO OTHER AD1556s AIN (–) R2 R4 DGND 31 16 SYNC HARDWARE 25 +V AGND1 –V A AGND2 A CONTROL RESET 3, 26 1 27 4, 20, 21 RESETD 37 10 +5V –5V H/S 100nF 100nF V 10 F 10 F L DGND 11, 22, 44 100nF 12, 23, 24, 34 VDIG
Figure 7. Typical Operating Circuit –16– REV. B