Datasheet AD7810 (Analog Devices) - 10

AD7810 Mode 2 Operation (Automatic Power-Down)
before initiating a serial read. The serial port of the AD7810 is When used in this mode of operation, the part automatically still functional even though the AD7810 has been powered down. powers down at the end of a conversion. This is achieved by NOTE: Serial read should not cross the next rising edge of leaving the CONVST signal low until the end of the conversion. CONVST. Because it takes approximately 1.5 µs for the part to power up Because it is possible to do a serial read from the part while it after it has been powered down, this mode of operation is in- is powered down, the AD7810 is powered up only to do the tended to be used in applications where slower throughput rates conversion and is immediately powered down at the end of a are required, i.e., in the order of 100 kSPS. The timing diagram conversion. This significantly improves the power consumption in Figure 15 shows how to operate the part in this mode. If the of the part at slower throughput rates—see Power vs. Through- AD7810 is powered down, the rising edge of the CONVST put Rate section. pulse causes the part to power up. When the part has powered up (≈ 1.5 µs after the rising edge of CONVST), the CONVST
SERIAL INTERFACE
signal is brought low, and a conversion is initiated on this falling The serial interface of the AD7810 consists of three wires, a edge of the CONVST signal. The conversion takes 2.3 µs and serial clock input SCLK, serial port enable CONVST and a after this time, the conversion result is latched into the serial serial data output DOUT (see Figure 16). The serial interface shift register and the part powers down. Therefore, when the is designed to allow easy interfacing to most microcontrollers, part is operated in Mode 2, the effective conversion time is e.g., PIC16C, PIC17C, QSPI and SPI, without the need for any equal to the power-up time (1.5 µs) and the SAR conversion gluing logic. When interfacing to the 8051, the SCLK must be time (2.3 µs). inverted. The Microprocessor Interface section explains how to NOTE: Although the AD7810 takes 1.5 µs to power up after the interface to some popular microcontrollers. rising edge of CONVST, it is not necessary to leave CONVST Figure 16 shows the timing diagram for a serial read from the high for 1.5 µs after the rising edge before bringing it low to AD7810. The serial interface works with both a continuous and initiate a conversion. If the CONVST signal goes low before 1.5 µs a noncontinuous serial clock. The rising edge of the CONVST in time has elapsed, then the power-up time is timed out inter- signal resets a counter, which counts the number of serial clocks nally and a conversion is then initiated. Hence the AD7810 is to ensure the correct number of bits are shifted out of the serial guaranteed to have always powered up before a conversion is shift registers. The SCLK is ignored once the correct number of initiated—even if the CONVST pulsewidth is < 1.5 µs. If the bits have been shifted out. In order for another serial transfer to CONVST width is > 1.5 µs, then a conversion is initiated on take place, the counter must be reset by the falling edge of the the falling edge. 10th SCLK. Data is clocked out from the DOUT line on the first As in the case of Mode 1 operation, the rising edge of the rising SCLK edge after the rising edge of the CONVST signal CONVST pulse enables the serial port of the AD7810 (see and on subsequent SCLK rising edges. DOUT enters its high Serial Interface section). If a serial read is initiated soon after impedance state again on the falling edge of the 10th SCLK. this rising edge (Point “A”), i.e., before the end of the conver- In multipackage applications, the CONVST signal can be used sion, the result of the previous conversion is shifted out on pin as a chip select signal. The serial interface will not shift data out DOUT. In order to read the result of the current conversion, the until it receives a rising edge on the CONVST pin. user must wait at least 2.3 µs after the falling edge of CONVST
tPOWER-UP t 1.5
␮
s 1 CONVST SCLK A B DOUT CURRENT CONVERSION RESULT
Figure 15. Mode 2 Operation Timing
t3 SCLK 1 2 3 4 5 6 7 8 9 10 t t 5 4 CONVST t t 7 t8 6 DOUT DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Figure 16. AD7810 Serial Interface Timing REV. B –9–