Datasheet AD7892 (Analog Devices) - 8
| Fabricante | Analog Devices |
| Descripción | True Bipolar Input, Single Supply, Parallel, 12-Bit 600 kSPS ADC |
| Páginas / Página | 15 / 8 — AD7892. Pin No. Mnemonic. Description. PIN CONFIGURATION. DIP and SOIC. … |
| Revisión | C |
| Formato / tamaño de archivo | PDF / 177 Kb |
| Idioma del documento | Inglés |
AD7892. Pin No. Mnemonic. Description. PIN CONFIGURATION. DIP and SOIC. VDD 1. 24 CONVST. STANDBY. 23 EOC. VIN2 3. 22 CS. VIN1 4. 21 RD
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AD7892 Pin No. Mnemonic Description
16 DB4/SCLK Data Bit 4/Serial Clock. When the device is in its parallel mode, this pin is Data Bit 4, a three-state TTL-compatible output. When the device is in its serial mode, this becomes the serial clock pin, SCLK. SCLK is an input and an external serial clock must be provided at this pin to obtain serial data from the AD7892. Serial data is clocked out from the output shift register on the rising edges of SCLK after RFS goes low. 17 DB3/RFS Data Bit 3/Receive Frame Synchronization. When the device is in its parallel mode, this pin is Data Bit 3, a three-state TTL-compatible output. When the device is in its serial mode, this becomes the receive frame synchronization input with RFS provided externally to obtain serial data from the AD7892. 18 DB2 Data Bit 2. Three-state TTL-compatible output. This output should be left unconnected when the device is in its serial mode. 19 DB1 Data Bit 1. Three-state TTL-compatible output. This output should be left unconnected when the device is in its serial mode. 20 DB0 Data Bit 0 (LSB). Three-state TTL-compatible output. Output coding is two’s complement for AD7892-1 and AD7892-3 and straight (natural) binary for AD7892-2. This output should be left unconnected when the device is in its serial mode. 21 RD Read. Active low logic input which is used in conjunction with CS low to enable the data outputs. 22 CS Chip Select. Active low logic input which is used in conjunction with RD to enable the data outputs. 23 EOC End-of-Conversion. Active low logic output indicating converter status. The end of conversion is signified by a low going pulse on this line. The duration of this EOC pulse is nominally 100 ns. 24 CONVST Convert Start. Logic Input. A low-to-high transition on this input puts the track/hold into its hold mode and starts conversion.
PIN CONFIGURATION DIP and SOIC VDD 1 24 CONVST STANDBY 2 23 EOC VIN2 3 22 CS VIN1 4 21 RD REF OUT/REF IN 5 20 DB0 (LSB) AGND 6 AD7892 19 DB1 TOP VIEW MODE 7 18 DB2 (Not to Scale) DB11/LOW 8 17 DB3/RFS DB10/LOW 9 16 DB4/SCLK DB9 10 15 DB5/SDATA DB8 11 14 DGND DB7 12 13 DB6
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16 DB4/SCLK Data Bit 4/Serial Clock. When the device is in its parallel mode, this pin is Data Bit 4, a three-state TTL-compatible output. When the device is in its serial mode, this becomes the serial clock pin, SCLK. SCLK is an input and an external serial clock must be provided at this pin to obtain serial data from the AD7892. Serial data is clocked out from the output shift register on the rising edges of SCLK after RFS goes low. 17 DB3/RFS Data Bit 3/Receive Frame Synchronization. When the device is in its parallel mode, this pin is Data Bit 3, a three-state TTL-compatible output. When the device is in its serial mode, this becomes the receive frame synchronization input with RFS provided externally to obtain serial data from the AD7892. 18 DB2 Data Bit 2. Three-state TTL-compatible output. This output should be left unconnected when the device is in its serial mode. 19 DB1 Data Bit 1. Three-state TTL-compatible output. This output should be left unconnected when the device is in its serial mode. 20 DB0 Data Bit 0 (LSB). Three-state TTL-compatible output. Output coding is two’s complement for AD7892-1 and AD7892-3 and straight (natural) binary for AD7892-2. This output should be left unconnected when the device is in its serial mode. 21 RD Read. Active low logic input which is used in conjunction with CS low to enable the data outputs. 22 CS Chip Select. Active low logic input which is used in conjunction with RD to enable the data outputs. 23 EOC End-of-Conversion. Active low logic output indicating converter status. The end of conversion is signified by a low going pulse on this line. The duration of this EOC pulse is nominally 100 ns. 24 CONVST Convert Start. Logic Input. A low-to-high transition on this input puts the track/hold into its hold mode and starts conversion.
PIN CONFIGURATION DIP and SOIC VDD 1 24 CONVST STANDBY 2 23 EOC VIN2 3 22 CS VIN1 4 21 RD REF OUT/REF IN 5 20 DB0 (LSB) AGND 6 AD7892 19 DB1 TOP VIEW MODE 7 18 DB2 (Not to Scale) DB11/LOW 8 17 DB3/RFS DB10/LOW 9 16 DB4/SCLK DB9 10 15 DB5/SDATA DB8 11 14 DGND DB7 12 13 DB6
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