Datasheet AD5686, AD5684 (Analog Devices) - 6

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AD5686/AD5684 Data Sheet TIMING CHARACTERISTICS
All input signals are specified with tR = tF = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. See Figure 2. VDD = 2.7 V to 5.5 V, 1.62 V ≤ VLOGIC ≤ 5.5 V; VREF = 2.5 V. All specifications TMIN to TMAX, unless otherwise noted.
Table 4. 1.62 V ≤ VLOGIC < 2.7 V 2.7 V ≤ VLOGIC ≤ 5.5 V Parameter1 Symbol Min Max Min Max Unit
SCLK Cycle Time t1 20 20 ns SCLK High Time t2 10 10 ns SCLK Low Time t3 10 10 ns SYNC to SCLK Falling Edge Setup Time t4 15 10 ns Data Setup Time t5 5 5 ns Data Hold Time t6 5 5 ns SCLK Falling Edge to SYNC Rising Edge t7 10 10 ns Minimum SYNC High Time t8 20 20 ns SYNC Rising Edge to SYNC Rising Edge (DAC Register Update/s) t9 870 830 ns SYNC Falling Edge to SCLK Fall Ignore t10 16 10 ns LDAC Pulse Width Low t11 15 15 ns SYNC Rising Edge to LDAC Rising Edge t12 20 20 ns SYNC Rising Edge to LDAC Falling Edge t13 30 30 ns LDAC Falling Edge to SYNC Rising Edge t14 840 800 ns Minimum Pulse Width Low t15 30 30 ns Pulse Activation Time t16 30 30 ns Power-Up Time2 4.5 4.5 µs 1 Maximum SCLK frequency is 50 MHz at VDD = 2.7 V to 5.5 V, 1.62 V ≤ VLOGIC ≤ VDD. Guaranteed by design and characterization; not production tested. 2 Time to exit power-down to normal mode of AD5686/AD5684 operation, SYNC rising edge to 90% of DAC midscale value, with output unloaded.
t10 t1 SCLK t2 t8 t t 3 7 t14 t4 SYNC t9 t6 t5 SDIN DB23 DB0 t11 t13 LDAC1 t12 LDAC2 RESET t15 t V 16 OUT 1ASYNCHRONOUS LDAC UPDATE MODE.
002
2SYNCHRONOUS LDAC UPDATE MODE.
10797- Figure 2. Serial Write Operation Rev. C | Page 6 of 27 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS AC CHARACTERISTICS TIMING CHARACTERISTICS DAISY-CHAIN AND READBACK TIMING CHARACTERISTICS Circuit and Timing Diagrams ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION DIGITAL-TO-ANALOG CONVERTER TRANSFER FUNCTION DAC ARCHITECTURE Output Amplifiers SERIAL INTERFACE Input Shift Register STANDALONE OPERATION WRITE AND UPDATE COMMANDS Write to Input Register n (Dependent on LDACB) Update DAC Register n with Contents of Input Register n Write to and Update DAC Channel n (Independent of LDACB) DAISY-CHAIN OPERATION READBACK OPERATION POWER-DOWN OPERATION LOAD DAC (HARDWARE LDACB PIN) Instantaneous DAC Updating (LDACB Held Low) Deferred DAC Updating (LDACB Is Pulsed Low) LDACB MASK REGISTER HARDWARE RESET (RESETB) RESET SELECT PIN (RSTSEL) APPLICATIONS INFORMATION MICROPROCESSOR INTERFACING AD5686/AD5684 TO ADSP-BF531 INTERFACE AD5686/AD5684 TO SPORT INTERFACE LAYOUT GUIDELINES GALVANICALLY ISOLATED INTERFACE OUTLINE DIMENSIONS ORDERING GUIDE