Datasheet AD8318 (Analog Devices) - 20

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Data Sheet AD8318
In many log amp applications, it may be necessary to lower the The basic connections for operating the AD8318 as an analog corner frequency of the postdemodulation filtering to achieve control er with the AD8367 are shown in Figure 43. The low output ripple while maintaining a rapid response time to AD8367 is a low frequency to 500 MHz VGA with 45 dB of changes in signal level. For an example of a 4-pole active filter, dynamic range. This configuration is very similar to the one see the AD8307 data sheet. shown in Figure 42. For applications working at high input
CONTROLLER MODE
frequencies, such as cellular bands or WLAN, or those requiring large gain control ranges, the AD8318 can control The AD8318 provides a control er mode feature at the VOUT the 10 MHz to 3 GHz ADL5330 RF VGA. For further details pin. Using VSET for the setpoint voltage, it is possible for the and an application schematic, refer to the ADL5330 data sheet. AD8318 to control subsystems, such as power amplifiers (PAs), variable gain amplifiers (VGAs), or variable voltage attenuators The voltage applied to the GAIN pin controls the gain of the (VVAs) that have output power that increases monotonically AD8367. This voltage, VGAIN, is scaled linear-in-dB with a slope with respect to their gain control signal. of 20 mV/dB and runs from 50 mV at −2.5 dB of gain up to 1.0 V at +42.5 dB. To operate in control er mode, the link between VSET and VOUT is broken. A setpoint voltage is applied to the VSET The incoming RF signal to the AD8367 has a varying amplitude input; VOUT is connected to the gain control terminal of the level. Receiving and demodulating it with the lowest possible VGA, and the detector RF input is connected to the output of error requires that the signal levels be optimized for the highest the VGA (usually using a directional coupler and some signal-to-noise ratio (SNR) feeding into the analog-to-digital additional attenuation). Based on the defined relationship converters (ADC). This is done by using an automatic gain between V control (AGC) loop. In Figure 43, the voltage output of the OUT and the RF input signal when the device is in measurement mode, the AD8318 adjusts the voltage on VOUT AD8318 modifies the gain of the AD8367 until the incoming (VOUT is now an error amplifier output) until the level at the RF signal produces an output voltage that is equal to the RF input corresponds to the applied V setpoint voltage VSET. SET.
+3V
When the AD8318 operates in control er mode, there is no
RF INPUT SIGNAL RF OUTPUT SIGNAL
defined relationship between V
VPOS GND
SET and VOUT voltage; VOUT settles
0.1µF
to a value that results in the correct input signal level appearing
174Ω INPT AD8367 VOUT VGA
at INHI/INLO.
57.6Ω GAIN HPFL
In order for this output power control loop to be stable, a
CHP 100pF
ground-referenced capacitor is connected to the CLPF pin.
R2 R 261Ω HP R1 +5V 100MHz 100Ω 1kΩ BANDPASS
This capacitor, C
FILTER
FLT, integrates the error signal (in the form of a
VOUT VPOS 1nF
current) to set the loop bandwidth and ensure loop stability. For
+VSET DAC VSET INHI SETPOINT
further details on control loop dynamics, refer to the AD8315
AD8318 VOLTAGE INLO
data sheet.
CLPF C GND 1nF FLT
047
100pF
04853- Figure 43. AD8318 Operating in Controller Mode to Provide Automatic Gain
VGA/VVA RFIN
Control Functionality in Combination with the AD8367
DIRECTIONAL COUPLER
The AGC loop is capable of controlling signals over ~45 dB
GAIN CONTROL
dynamic range. The output of the AD8367 is designed to drive
ATTENUATOR VOLTAGE
loads ≥ 200 Ω. As a result, it is not necessary to use the 53.6 Ω
1nF VOUT
resistor at the input of the AD8318; the nominal input imped-
INHI
ance of 2 kΩ is sufficient.
52.3Ω AD8318 VSET DAC
If the AD8367 output drives a 50 Ω load, such as an oscil oscope
INLO 1nF CLPF
or spectrum analyzer, use a simple resistive divider network. The divider used in Figure 43 has an insertion loss of 11.5 dB. 034
CFLT
Figure 44 shows the transfer function of output power vs. VSET 04853- Figure 42. AD8318 Controller Mode voltage for a 100 MHz sine wave at −40 dBm into the AD8367. Decreasing VSET, which corresponds to demanding a higher signal from the VGA, tends to increase VOUT. The gain control voltage of the VGA must have a positive sense. A positive control voltage to the VGA increases the gain of the device. Rev. C | Page 19 of 24 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION USING THE AD8318 BASIC CONNECTIONS ENABLE INTERFACE INPUT SIGNAL COUPLING OUTPUT INTERFACE SETPOINT INTERFACE TEMPERATURE COMPENSATION OF OUTPUT VOLTAGE TEMPERATURE SENSOR MEASUREMENT MODE DEVICE CALIBRATION AND ERROR CALCULATION SELECTING CALIBRATION POINTS TO IMPROVE ACCURACY OVER A REDUCED RANGE VARIATION IN TEMPERATURE DRIFT FROM DEVICE TO DEVICE TEMPERATURE DRIFT AT DIFFERENT TEMPERATURES SETTING THE OUTPUT SLOPE IN MEASUREMENT MODE RESPONSE TIME CAPABILITY OUTPUT FILTERING CONTROLLER MODE CHARACTERIZATION SETUP AND METHODS EVALUATION BOARD OUTLINE DIMENSIONS ORDERING GUIDE