Datasheet LTC6903, LTC6904 (Analog Devices) - 10
| Fabricante | Analog Devices |
| Descripción | 1kHz - 68MHz Serial Port Programmable Oscillator |
| Páginas / Página | 14 / 10 — applicaTions inForMaTion Output Control. Serial Port Register … |
| Formato / tamaño de archivo | PDF / 246 Kb |
| Idioma del documento | Inglés |
applicaTions inForMaTion Output Control. Serial Port Register Description. LTC6903 SPI Compatible Interface
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LTC6903/LTC6904
applicaTions inForMaTion Output Control Serial Port Register Description
The CLK and CLK outputs of the LTC6903/LTC6904 are OCT[3:0] – Frequency Divider Setting. (See Frequency individually controllable through the serial port as de- Setting Information Section) scribed in Table 2 below. The low power mode may also DAC[9:0] – Master Oscillator Frequency Setting. (See be accessed through these control bits. It is preferred Frequency Setting Information Section) that unused outputs be disabled in order to reduce power dissipation and improve accuracy. CNF[1:0] – Output Configuration. This controls outputs CLK and CLK according to Table 2. Disabling an unused output will improve accuracy of operation at frequencies above 1MHz. An unused output
LTC6903 SPI Compatible Interface
running with no load typically degrades frequency ac- curacy up to 0.2% at 68MHz. An unused output running A serial data transfer is composed of sixteen (16) bits of into a 5pF load typically degrades frequency accuracy up data labeled D15 through D0. D15 is the first bit of data to 0.5% at 68MHz. presented in each transaction. All serial port register bits are set LOW on power-up.
Table 2. Output Configuration CNF1 CNF0 CLK CLK Writing Data (LTC6903 Only)
0 0 ON CLK + 180° When the SEN line is brought LOW, serial data presented 0 1 OFF ON on the SDI input is clocked in on the rising edges of SCK 1 0 ON OFF until SEN is brought HIGH. On every eighth rising edge 1 1 Powered-Down* of SCK, the preceding 8-bits of data are clocked into the *Powered-Down: When in this mode, the chip is in a low power state internal register. It is therefore possible to clock in only and will require approximately 100µs to recover. This is not the same effect as the OE pin, which is fast, but uses more power supply current. the 8 {D15 - D8} most significant bits of data rather than completing an entire transfer.
Serial Port Bitmap (LTC6903/LTC6904)
The serial data transfer starts with the most significant (All serial port register bits default LOW at power up) bit and ends with the least significant bit of the data, as
Table 3
shown in the Timing Diagrams section.
D15 D14 D13 D12 D11 D10 D9 D8
OCT3 OCT2 OCT1 OCT0 DAC9 DAC8 DAC7 DAC6
D7 D6 D5 D4 D3 D2 D1 D0
DAC5 DAC4 DAC3 DAC2 DAC1 DAC0 CNF1 CNF0 69034fe 10 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Power Requirements Serial Port Electrical Characteristics Timing Characteristics Typical Performance Characteristics Pin Functions Block Diagram Timing Diagrams Theory of Operation Applications Information Package Description Revision History Typical Application Related Parts
applicaTions inForMaTion Output Control Serial Port Register Description
The CLK and CLK outputs of the LTC6903/LTC6904 are OCT[3:0] – Frequency Divider Setting. (See Frequency individually controllable through the serial port as de- Setting Information Section) scribed in Table 2 below. The low power mode may also DAC[9:0] – Master Oscillator Frequency Setting. (See be accessed through these control bits. It is preferred Frequency Setting Information Section) that unused outputs be disabled in order to reduce power dissipation and improve accuracy. CNF[1:0] – Output Configuration. This controls outputs CLK and CLK according to Table 2. Disabling an unused output will improve accuracy of operation at frequencies above 1MHz. An unused output
LTC6903 SPI Compatible Interface
running with no load typically degrades frequency ac- curacy up to 0.2% at 68MHz. An unused output running A serial data transfer is composed of sixteen (16) bits of into a 5pF load typically degrades frequency accuracy up data labeled D15 through D0. D15 is the first bit of data to 0.5% at 68MHz. presented in each transaction. All serial port register bits are set LOW on power-up.
Table 2. Output Configuration CNF1 CNF0 CLK CLK Writing Data (LTC6903 Only)
0 0 ON CLK + 180° When the SEN line is brought LOW, serial data presented 0 1 OFF ON on the SDI input is clocked in on the rising edges of SCK 1 0 ON OFF until SEN is brought HIGH. On every eighth rising edge 1 1 Powered-Down* of SCK, the preceding 8-bits of data are clocked into the *Powered-Down: When in this mode, the chip is in a low power state internal register. It is therefore possible to clock in only and will require approximately 100µs to recover. This is not the same effect as the OE pin, which is fast, but uses more power supply current. the 8 {D15 - D8} most significant bits of data rather than completing an entire transfer.
Serial Port Bitmap (LTC6903/LTC6904)
The serial data transfer starts with the most significant (All serial port register bits default LOW at power up) bit and ends with the least significant bit of the data, as
Table 3
shown in the Timing Diagrams section.
D15 D14 D13 D12 D11 D10 D9 D8
OCT3 OCT2 OCT1 OCT0 DAC9 DAC8 DAC7 DAC6
D7 D6 D5 D4 D3 D2 D1 D0
DAC5 DAC4 DAC3 DAC2 DAC1 DAC0 CNF1 CNF0 69034fe 10 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Power Requirements Serial Port Electrical Characteristics Timing Characteristics Typical Performance Characteristics Pin Functions Block Diagram Timing Diagrams Theory of Operation Applications Information Package Description Revision History Typical Application Related Parts