Datasheet MCP616, MCP617, MCP618, MCP619 (Microchip) - 10

MCP616/7/8/9 Note:
Unless otherwise indicated, VDD = +2.3V to +5.5V, VSS = GND, TA = 25°C, VCM = VDD/2, VOUT ≈ VDD/2, RL = 100 kΩ to VDD/2 and CL = 60 pF.
25 ) 1,000 V VDD = 2.3V (m t 20 oom rren ier) 100 15 V t Cu DD – VOH VDD = 5.5V 10 T A/Amplif A = +85°C iescen ltage Headr (µ T 10 A = +25°C o VOL – VSS Qu 5 TA = -40°C tput V u 0 O 1 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 10µ 100µ 1m 10m 0.01 0.1 1 10 Power Supply Voltage (V) Output Current Magnitude (A) FIGURE 2-19:
Quiescent Current vs.
FIGURE 2-22:
Output Voltage Headroom Power Supply Voltage. vs. Output Current Magnitude.
130 125 RL = 25 k 125 120 120 115 VDD = 5.5V 110 115 105 VDD = 2.3V 100 110 DC Open-Loop Gain (dB) 95 DC Open-Loop Gain (dB) 105 90 100 1k 10k 100k 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 0.1 1 10 100 Load Resistance (
Ω
) Power Supply Voltage (V) FIGURE 2-20:
DC Open-Loop Gain vs.
FIGURE 2-23:
DC Open-Loop Gain vs. Load Resistance. Power Supply Voltage.
200 100 140 Referred to Input 180 90 GBWP 130 160 80 ) 140 70 (° 120 in 120 60 g 110 100 PM 50 (kHz) 100 80 40 ase Mar 60 30 h 90 P Seperation (dB) 40 20 Channel-to-Channel Gain Bandwidth Product 80 20 10 0 0 70 1k 10k 100k 1M 100 1k 10k 100k 1 10 100 1,000 1.E+02 1.E+03 1.E+04 1.E+05 Load Resistance (
Ω
) Frequency (Hz) FIGURE 2-21:
Gain-Bandwidth Product,
FIGURE 2-24:
Channel-to-Channel Phase Margin vs. Load Resistance. Separation vs. Frequency (MCP617 and MCP619 only). DS21613C-page 10 © 2008 Microchip Technology Inc. Document Outline 1.0 Electrical Characteristics FIGURE 1-1: Timing Diagram for the CS Pin on the MCP618. 1.1 Test Circuits FIGURE 1-2: AC and DC Test Circuit for Most Non-Inverting Gain Conditions. FIGURE 1-3: AC and DC Test Circuit for Most Inverting Gain Conditions. 2.0 Typical Performance Curves FIGURE 2-1: Input Offset Voltage at VDD = 5.5V. FIGURE 2-2: Input Offset Voltage at VDD = 2.3V. FIGURE 2-3: Input Bias Current at VDD = 5.5V. FIGURE 2-4: Input Offset Voltage Drift at VDD = 5.5V. FIGURE 2-5: Input Offset Voltage Drift at VDD = 2.3V. FIGURE 2-6: Input Offset Current at VDD = 5.5V. FIGURE 2-7: Input Offset Voltage vs. Ambient Temperature. FIGURE 2-8: Quiescent Current vs. Ambient Temperature. FIGURE 2-9: Maximum Output Voltage Swing vs. Ambient Temperature at RL = 5 kW. FIGURE 2-10: Input Bias, Offset Currents vs. Ambient Temperature. FIGURE 2-11: CMRR, PSRR vs. Ambient Temperature. FIGURE 2-12: Maximum Output Voltage Swing vs. Ambient Temperature at RL = 25 kW. FIGURE 2-13: Output Short Circuit Current vs. Ambient Temperature. FIGURE 2-14: Slew Rate vs. Ambient Temperature. FIGURE 2-15: Input Bias, Offset Currents vs. Common Mode Input Voltage. FIGURE 2-16: Gain Bandwidth Product, Phase Margin vs. Ambient Temperature. FIGURE 2-17: Input Offset Voltage vs. Common Mode Input Voltage. FIGURE 2-18: Input Offset Voltage vs. Output Voltage. FIGURE 2-19: Quiescent Current vs. Power Supply Voltage. FIGURE 2-20: DC Open-Loop Gain vs. Load Resistance. FIGURE 2-21: Gain-Bandwidth Product, Phase Margin vs. Load Resistance. FIGURE 2-22: Output Voltage Headroom vs. Output Current Magnitude. FIGURE 2-23: DC Open-Loop Gain vs. Power Supply Voltage. FIGURE 2-24: Channel-to-Channel Separation vs. Frequency (MCP617 and MCP619 only). FIGURE 2-25: Open-Loop Gain, Phase vs. Frequency. FIGURE 2-26: Input Noise Voltage, Current Densities vs. Frequency. FIGURE 2-27: Small-Signal, Non-Inverting Pulse Response. FIGURE 2-28: CMRR, PSRR vs. Frequency. FIGURE 2-29: Maximum Output Voltage Swing vs. Frequency. FIGURE 2-30: Small-Signal, Inverting Pulse Response. FIGURE 2-31: Large-Signal, Non-Inverting Pulse Response. FIGURE 2-32: Chip Select (CS) to Amplifier Output Response Time (MCP618 only). FIGURE 2-33: The MCP616/7/8/9 Show No Phase Reversal. FIGURE 2-34: Large-Signal, Inverting Pulse Response. FIGURE 2-35: Chip Select (CS) Internal Hysteresis (MCP618 only). FIGURE 2-36: Measured Input Current vs. Input Voltage (below VSS). 3.0 Pin Descriptions TABLE 3-1: Pin Function Table 3.1 Analog Outputs 3.2 Analog Inputs 3.3 Chip Select Digital Input (CS) 3.4 Power Supply Pins (VDD, VSS) 4.0 Applications Information 4.1 Rail-to-Rail Inputs FIGURE 4-1: Simplified Analog Input ESD Structures. FIGURE 4-2: Protecting the Analog Inputs. 4.2 DC Offsets FIGURE 4-3: Example Circuit for Calculating DC Offset. FIGURE 4-4: Equivalent DC Circuit. 4.3 Rail-to-Rail Output 4.4 Capacitive Loads FIGURE 4-5: Output Resistor, RISO stabilizes large capacitive loads. FIGURE 4-6: Recommended RISO Values for Capacitive Loads. 4.5 MCP618 Chip Select (CS) 4.6 Supply Bypass 4.7 Unused Op Amps FIGURE 4-7: Unused Op Amps. 4.8 PCB Surface Leakage FIGURE 4-8: Example Guard Ring Layout for Inverting Gain. 4.9 Application Circuits FIGURE 4-9: High Gain Pre-amplifier. FIGURE 4-10: Two-Op Amp Instrumentation Amplifier. FIGURE 4-11: Three-Op Amp Instrumentation Amplifier. FIGURE 4-12: Precision Gain with Good Load Isolation. 5.0 Design Aids 5.1 SPICE Macro Model 5.2 Mindi™ Circuit Designer & Simulator 5.3 Microchip Advanced Part Selector (MAPS) 5.4 Analog Demonstration and Evaluation Boards 5.5 Application Notes 6.0 Packaging Information 6.1 Package Marking Information