Datasheet ADIS16135 (Analog Devices) - 5
| Fabricante | Analog Devices |
| Descripción | ±300°/Sec Precision Angular Rate Sensor |
| Páginas / Página | 21 / 5 — ADIS16135. Data Sheet. TIMING SPECIFICATIONS. Table 2. Normal Mode. … |
| Revisión | F |
| Formato / tamaño de archivo | PDF / 590 Kb |
| Idioma del documento | Inglés |
ADIS16135. Data Sheet. TIMING SPECIFICATIONS. Table 2. Normal Mode. Parameter Description. Min1 Typ Max Unit. TIMING DIAGRAMS. tCS. tSFS
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ADIS16135 Data Sheet TIMING SPECIFICATIONS
TA = 25°C, VCC = 5 V, unless otherwise noted.
Table 2. Normal Mode Parameter Description Min1 Typ Max Unit
fSCLK Serial clock 0.01 2.0 MHz tSTALL Stall period between data 9 μs tREADRATE Read rate 25 μs t Chip select to clock edge 48.8 ns CS tDAV DOUT valid after SCLK edge 25 ns tDSU DIN setup time before SCLK rising edge 24.4 ns tDHD DIN hold time after SCLK rising edge 48.8 ns tSCLKR, tSCLKF SCLK rise/fall times 5 12.5 ns tDR, tDF DOUT rise/fall times 5 12.5 ns tSFS CS high after SCLK edge 0 ns t1 Input sync positive pulse width 5 μs tx Input sync low time 100 μs t2 Input sync to data ready output 360 μs t3 Input sync period 488 μs 1 Guaranteed by design and characterization but not tested in production.
TIMING DIAGRAMS CS tCS tSFS 1 2 3 4 5 6 15 16 SCLK tDAV DOUT MSB DB14 DB13 DB12 DB11 DB10 DB2 DB1 LSB t t DSU DHD DIN R/W A6 A5 A4 A3 A2 D2 D1 LSB
02 0 8- 888 0 Figure 2. SPI Timing and Sequence
tREADRATE tSTALL CS SCLK
-003 888 08 Figure 3. Stall Time and Data Rate
t3 t2 t t 1 X SYNC CLOCK (CLKIN)
04
DATA
-0 88
READY
088 Figure 4. Input Clock Timing Diagram Rev. F | Page 4 of 20 Document Outline Features Applications General Description Functional Block Diagram Revision History Specifications Timing Specifications Timing Diagrams Absolute Maximum Ratings ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Basic Operation Reading Sensor Data Output Data Registers Rotation Rate (Gyroscope) Internal Temperature Dual Memory Structure User Registers Digital Processing Configuration Internal Sample Rate Input Clock Configuration Digital Filtering Averaging/Decimation Filter Calibration Automatic Bias Correction Manual Bias Correction Alarms Static Alarm Use Dynamic Alarm Use Alarm Reporting Alarm Example System Controls Global Commands Software Reset Memory Management Checksum Test General-Purpose I/O Data Ready I/O Indicator Example I/O Configuration Self-Test Power Management Status Product Identification Applications Information Breakout Board Installation Tips Outline Dimensions Ordering Guide
TA = 25°C, VCC = 5 V, unless otherwise noted.
Table 2. Normal Mode Parameter Description Min1 Typ Max Unit
fSCLK Serial clock 0.01 2.0 MHz tSTALL Stall period between data 9 μs tREADRATE Read rate 25 μs t Chip select to clock edge 48.8 ns CS tDAV DOUT valid after SCLK edge 25 ns tDSU DIN setup time before SCLK rising edge 24.4 ns tDHD DIN hold time after SCLK rising edge 48.8 ns tSCLKR, tSCLKF SCLK rise/fall times 5 12.5 ns tDR, tDF DOUT rise/fall times 5 12.5 ns tSFS CS high after SCLK edge 0 ns t1 Input sync positive pulse width 5 μs tx Input sync low time 100 μs t2 Input sync to data ready output 360 μs t3 Input sync period 488 μs 1 Guaranteed by design and characterization but not tested in production.
TIMING DIAGRAMS CS tCS tSFS 1 2 3 4 5 6 15 16 SCLK tDAV DOUT MSB DB14 DB13 DB12 DB11 DB10 DB2 DB1 LSB t t DSU DHD DIN R/W A6 A5 A4 A3 A2 D2 D1 LSB
02 0 8- 888 0 Figure 2. SPI Timing and Sequence
tREADRATE tSTALL CS SCLK
-003 888 08 Figure 3. Stall Time and Data Rate
t3 t2 t t 1 X SYNC CLOCK (CLKIN)
04
DATA
-0 88
READY
088 Figure 4. Input Clock Timing Diagram Rev. F | Page 4 of 20 Document Outline Features Applications General Description Functional Block Diagram Revision History Specifications Timing Specifications Timing Diagrams Absolute Maximum Ratings ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Basic Operation Reading Sensor Data Output Data Registers Rotation Rate (Gyroscope) Internal Temperature Dual Memory Structure User Registers Digital Processing Configuration Internal Sample Rate Input Clock Configuration Digital Filtering Averaging/Decimation Filter Calibration Automatic Bias Correction Manual Bias Correction Alarms Static Alarm Use Dynamic Alarm Use Alarm Reporting Alarm Example System Controls Global Commands Software Reset Memory Management Checksum Test General-Purpose I/O Data Ready I/O Indicator Example I/O Configuration Self-Test Power Management Status Product Identification Applications Information Breakout Board Installation Tips Outline Dimensions Ordering Guide