Datasheet KSZ8999 (Microchip) - 4

Micrel, Inc. KS8999 Contents
System Level Applications.6
Pin Configuration .7
Pin Description .8
I/O Grouping .14
I/O Description.14
Functional Overview: Physical Layer Transceiver .19
100BaseTX Transmit .19
100BaseTX Receive .19
PLL Clock Synthesizer.19
Scrambler/De-scrambler (100BaseTX only).19
100BaseFX Operation .19
100BaseFX Signal Detection.19
100BaseFX Far End Fault .19
10BaseT Transmit .19
10BaseT Receive .19
Power Management.20
Power Save Mode .20
MDI/MDI-X Auto Crossover .20
Auto-Negotiation .20
Functional Overview: Switch Core .21
Address Look-Up .21
Learning .21
Migration .21
Aging.21
Forwarding .21
Switching Engine .21
MAC Operation .22
Inter Packet Gap (IPG).22
Backoff Algorithm .22
Late Collision.22
Illegal Frames.22
Flow Control .22
Half Duplex Back Pressure .22
Broadcast Storm Protection.22
MII Interface Operation .23
SNI Interface (7-wire) Operation .25
Programmable Features .25
Priority Schemes.25
Per Port Method.25
802.1p Method.25
IPv4 DSCP Method.25
Other Priority Considerations.25
VLAN Operation.26
Station MAC Address (control frames only) .27
EEPROM Operation.27
Optional CPU Interface .28
January 2005 4 KS8999