Datasheet LTC3900 (Analog Devices) - 6
| Fabricante | Analog Devices |
| Descripción | Synchronous Rectifier Driver for Forward Converters |
| Páginas / Página | 20 / 6 — pin FuncTions. CS+, CS– (Pin 1, 2):. GND (Pin 6):. TIMER (Pin 7):. CG … |
| Formato / tamaño de archivo | PDF / 288 Kb |
| Idioma del documento | Inglés |
pin FuncTions. CS+, CS– (Pin 1, 2):. GND (Pin 6):. TIMER (Pin 7):. CG (Pin 3):. SYNC (Pin 8):. VCC (Pin 4):. FG (Pin 5):. block DiagraM
Línea de modelo para esta hoja de datos
Versión de texto del documento
LTC3900
pin FuncTions CS+, CS– (Pin 1, 2):
Current Sense Differential Input.
GND (Pin 6):
The VCC bypass capacitor should be con- Connect CS+ through a series resistor to the drain of the nected directly to this GND pin. external catch MOSFET, Q4. Connect CS– to the source.
TIMER (Pin 7):
Timer Input. Connect this pin to an external The LTC3900 monitors the CS inputs 250ns after CG goes R-C network to program the timeout period. The LTC3900 high. If the inductor current reverses and flows into the resets the timer at every negative transition of the SYNC MOSFET causing CS+ to rise above CS– by more than input. If the SYNC signal is missing or incorrect, the 10.5mV, the LTC3900 pulls CG low. See the Current Sense LTC3900 pulls both CG and FG low once the TIMER pin section for more details on choosing the resistance value goes above the timeout threshold. See the Timer section for RCS1 to RCS3. for more details on programming the timeout period.
CG (Pin 3):
Catch MOSFET Gate Driver. This pin drives the
SYNC (Pin 8):
Driver Synchronization Input. This input gate of the external N-channel catch MOSFET, Q4. is signal edge sensitive. A negative voltage slew at SYNC
VCC (Pin 4):
Main Supply Input. This pin powers the driv- forces FG to pull high and CG to pull low. A positive volt- ers and the rest of the internal circuitry. Bypass this pin age slew at SYNC forces FG to pull low and CG to pull to GND using a 4.7µF ceramic capacitor in close proximity high. The SYNC input can accept both pulse or square to the LTC3900. wave signals.
FG (Pin 5):
Forward MOSFET Gate Driver. This pin drives the gate of the external N-channel forward MOSFET, Q3.
block DiagraM
SYNC+ S+ 4 VCC +1.4V –1.4V SYNC– S– SYNC 8 SYNC 5 AND FG CS+ 1 IS DRIVER CS– 2 – + LOGIC DISABLE 10.5mV ZCS DRIVER 3 11V TIMER CG RESET TMR UVLO TIMER 7 R1 180k R2 ZTMR 45k 0.5 • VCC MTMR 3900 BD 6 GND 3900fb 6 Document Outline Features Description Applications Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Applications Information Typical Applications Package Description Revision History Typical Application Related Parts
pin FuncTions CS+, CS– (Pin 1, 2):
Current Sense Differential Input.
GND (Pin 6):
The VCC bypass capacitor should be con- Connect CS+ through a series resistor to the drain of the nected directly to this GND pin. external catch MOSFET, Q4. Connect CS– to the source.
TIMER (Pin 7):
Timer Input. Connect this pin to an external The LTC3900 monitors the CS inputs 250ns after CG goes R-C network to program the timeout period. The LTC3900 high. If the inductor current reverses and flows into the resets the timer at every negative transition of the SYNC MOSFET causing CS+ to rise above CS– by more than input. If the SYNC signal is missing or incorrect, the 10.5mV, the LTC3900 pulls CG low. See the Current Sense LTC3900 pulls both CG and FG low once the TIMER pin section for more details on choosing the resistance value goes above the timeout threshold. See the Timer section for RCS1 to RCS3. for more details on programming the timeout period.
CG (Pin 3):
Catch MOSFET Gate Driver. This pin drives the
SYNC (Pin 8):
Driver Synchronization Input. This input gate of the external N-channel catch MOSFET, Q4. is signal edge sensitive. A negative voltage slew at SYNC
VCC (Pin 4):
Main Supply Input. This pin powers the driv- forces FG to pull high and CG to pull low. A positive volt- ers and the rest of the internal circuitry. Bypass this pin age slew at SYNC forces FG to pull low and CG to pull to GND using a 4.7µF ceramic capacitor in close proximity high. The SYNC input can accept both pulse or square to the LTC3900. wave signals.
FG (Pin 5):
Forward MOSFET Gate Driver. This pin drives the gate of the external N-channel forward MOSFET, Q3.
block DiagraM
SYNC+ S+ 4 VCC +1.4V –1.4V SYNC– S– SYNC 8 SYNC 5 AND FG CS+ 1 IS DRIVER CS– 2 – + LOGIC DISABLE 10.5mV ZCS DRIVER 3 11V TIMER CG RESET TMR UVLO TIMER 7 R1 180k R2 ZTMR 45k 0.5 • VCC MTMR 3900 BD 6 GND 3900fb 6 Document Outline Features Description Applications Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Applications Information Typical Applications Package Description Revision History Typical Application Related Parts